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TI OMAP 4™ Platform QoS, Chip-to-Chip (C2C), and Debug

Contents:

 OMAP4 TRM L3 Interconnect is Arteris NoC

 

Copyright © 2010, Texas Instruments Incorporated

OMAP 4 Platform Quality of Service (QoS) and Security:  Bandwidth Regulators, Rate Adapters and Firewalls

Bandwidth Regulators

Texas Instruments Incorporated implements bandwidth regulators within the OMAP 4 L3 network-on-chip interconnect to prevent master IP cores from consuming more than their share of the bandwidth of a link, or a slave network interface unit (NIU) that is shared between several data flows. If this condition occurs, then packets are transported at a lower rate. The bandwidth regulator uses a pressure-level flow control scheme to regulate packet flow over the network-on-chip interconnect. (Source: OMAP 4430 TRM, page 2659)

Rate Adapters and FIFOs

Rate adapters and FIFOs are used at bandwidth discontinuities to ensure efficient use of connections. (Source:  OMAP 4430 TRM, page 2660)

Programmable Firewalls

Programmable firewalls are used within the L3 network-on-chip interconnect to protect IP blocks from unauthorized access. (Source: OMAP 4430 TRM, page 2660-2670)

OMAP 4430 processor Chip-to-Chip (C2C) low latency interface uses Arteris network-on-chip technology

According to the OMAP4430 TRM, the chip-to-chip (C2C) block is a serial, low-latency, peer-to-peer communication protocol that enables the extension of an internal protocol bus to one physical device over a printed circuit board (PCB). (Source: OMAP 4430 TRM, page 2816) The purpose of this block is to allow low latency connection to a mobile phone modem through a low pin count interface.

TI OMAP 4 Chip-to-Chip (C2C) low latency interchip link Arteris NoC Copyright © 2010, Texas Instruments Incorporated. Reprinted with permission.
Source: OMAP 4430 TRM, page 2816

Debug and profiling features available through the OMAP 4430 processor L3 network-on-chip interconnect

There are many options available for hardware and software debug through the L3 network-on-chip interconnect:

  • 5 OCP watchpoint probes to monitor request flow  (Source:  TRM, page 5290)
  • NoC Statistics Collector computes traffic statistics within a user-defined window and periodically reports to the user through the MIPI-STM interface. Collectors are available for SDRAM load monitoring and master latency monitoring. (Source:  TRM, page 5291)
  • Statistics collected include:
    • Average burst length in bytes/packet per sampling window
    • Average throughput in bytes/cycle
    • % Link occupancy on the request link (for store transactions) during a sampling window
    • % Link occupancy on the response link (for load transactions) during a sampling window
    • % Arbitration conflict cycles on the request link
    • % Initiator busy cycles on the response link
    • Histogram of payload length in bytes (for example, 0–16 , 16–32, 32–128) each sampling window.
    • Histogram of quality of service

 

Note: "OMAP 4430 TRM" refers to Texas Instruments Incorporated's “Technical Reference Manual: OMAP4430 Multimedia Device, Silicon Revision 2.x, Version K” document, Copyright © 2010, Texas Instruments Incorporated. Portions reprinted with permission.

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