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TI OMAP™ 4 Platform and Arteris Network-on-Chip IP

Texas Instruments Incorporated uses Arteris network-on-chip interconnect IP as the main interconnect within OMAP™ 4 processors as well as in the Chip-to-Chip Interface (C2C).

Details on TI’s implementation of these features are contained in these publicly available TI documents:

Contents:

OMAP4 TRM L3 Interconnect is Arteris NoC

 

Copyright © 2010, Texas Instruments Incorporated

TI OMAP 4 main L3 Interconnect is an instantiation of an Arteris Network-on-Chip Interconnect

As shown below in Chapter 13 of TI’s “Technical Reference Manual: OMAP4430 Multimedia Device, Silicon Revision 2.x, Version K” document, Arteris network-on-chip interconnect IP plays a critical role as the central nervous system within TI’s OMAP 4 products:

OMAP4 L3 Interconnect is Arteris FlexNoC Network on Chip IP
Copyright © 2010, Texas Instruments Incorporated. Reprinted with permission.
Source: OMAP 4430 TRM, page 2643

Main L3 Interconnect is used for high throughput connections

The L3 interconnect within OMAP 4 processors connects high throughput IP blocks, such as the dual ARM Cortex A9 CPU subsystem, the DSP subsystem, the IVA-HD image and video imaging hardware accelerator subsystem, the SGX 2D/3D graphics accelerator subsystem, the Chip-to-Chip (C2C) interface, and the memory subsystem.

The IP blocks attached to the OMAP 4 main L3 interconnect use many protocols, including OCP and AMBA AXI.

The L3 network-on-chip interconnect has three different clock domains (CLK1, CLK2, and CLK3). (Source:  TRM, page 2656)

TI OMAP 4430 L3 Interconnect High Bandwidth Arteris NoC
Copyright © 2010, Texas Instruments Incorporated. Reprinted with permission.
Source: OMAP 4430 TRM, page 2646

Note: "OMAP 4430 TRM" refers to Texas Instruments Incorporated's “Technical Reference Manual: OMAP4430 Multimedia Device, Silicon Revision 2.x, Version K” document, Copyright © 2010, Texas Instruments Incorporated. Portions reprinted with permission.

 

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