Arteris - Interconnect Fabric IP for SoCs
Arteris provides Network-on-Chip (NoC) interconnect semiconductor intellectual property (IP) to System on Chip (SoC) makers so they can reduce cycle time, increase margins, and easily add functionality. Arteris invented the industry's first commercial network on chip (NoC) SoC interconnect IP solutions and is the industry leader. Unlike traditional solutions, Arteris interconnect plug-and-play technology is flexible and efficient, allowing designers to optimize for throughput, power, latency and floorplan.
Arteris History & Timeline
Arteris is different because we were founded by networking experts who applied their knowledge to the problems of SoC development. As SoC makers added more IP blocks to chips, traditional bus and crossbar means to communication became very inefficient, resulting in serious pain to architects, designers, and integrators: Massive numbers of wires, failed timing closure, increased heat and power consumption, and spaghetti-like routing congestion leading to increased die area. These problems were compounded when there were IP changes late in the design cycle or when management expected the next derivative version of the chip to be on time and risk free because only a few IP blocks were changed.
Arteris On-Chip Interconnect Technology
The Arteris Network-on-Chip (NoC) architecture borrows concepts from the computer networking arena and adapts them to system-on-chip design constraints. The network on chip solution optimizes performance, silicon area, and power, and reflects an in-depth understanding and integration of the constraints imposed by SoC implementations and semiconductor processes. By removing the inherent architectural limitations of traditional interconnect solutions, Arteris Network-on-Chip semiconductor IP offers a quantum leap in design quality and productivity, allowing SoC designers to achieve their ultimate design goals faster, easier and with less cost.
Arteris pioneered the first commercial NoC SoC offering, led the mass market adoption of Network-on-Chip solutions, and is the market leader in this space. There have been over 50 tapeouts of systems-on-chip using Arteris network-on-chip interconnect IP.
Key benefits of Arteris network-on-chip interconnect solutions include:
- Improved performance, power and silicon area
- Highly scalable to support a wide range of performance and complexity levels
- Easy-to-use solution for simple designs with a handful of IPs to complex SoCs with hundreds of IPs
- Plug-and-Play with IP using any transaction protocol - no IP lock-in
- Shortened development times with advanced tool suite and architecture features
- Architect-centric tools allow architects to increase their efficiency and value-add to the entire design team
- Providing certainty in tape out schedule by allowing faster and easier verification and timing closure
The Arteris interconnect IP offers us a convenient solution to handle the high speed communication needed between our SoC and external modem IC. Our customers will benefit from the lower BOM cost and power consumption as a result of this IP. We look forward to Arteris’ interconnect IP helping us shorten development schedules and lower risks associated with compatibility.
Thomas Kim, Vice President, SoC Platform Development, System LSI, Samsung Electronics