Arteris Articles

CES 2016: CPU, GPU or … VPU?

Winners, losers and observations from the Consumer Electronics Show

Where is the semiconductor industry going in the post-smartphone era? What trends are going to shape next-generation applications and SoC development?

Just by walking around the CES show floor this year, I would say advanced visual processing technology is the horse to put money on. It was everywhere, from ADAS systems, drones, to GoPro cameras, IP cameras with embedded facial recognition, motion detectors, virtual reality, augmented reality, displays and a whole lot more.

Topics: automotive semiconductors ADAS CPU GPU video

How is SSD flash memory like a helicopter?

It destroys itself as it is operating.*

Bear with me now as I explain how SSD flash memory works similar to helicopters...

First, let's explain the helicopter part of this analogy: Fixed wing aviators (i.e. non-helicopter pilots) are keen to remind people that the act of converting a jet engine's axial force into the orthogonal axis required to spin a helicopter rotor requires a sophisticated gearbox that slowly (and sometimes not so slowly) grinds itself to death through friction.

Topics: enterprise SSD flexnoc resilience package memory reliability

SemiEngineering: Memory Choices Grow

Editor's note: This is a great article by Ed Sperling at Semiconductor Engineering, so I have highlighted it here. Cache coherency in modern SoCs is discussed toward the middle of the article. -Kurt

Read the entire article at Semiconductor Engineering.


Memory Choices Grow

Memory is emerging as the starting point for SoCs, adding more confusion to already complex designs.

NOVEMBER 24TH, 2015 - BY: ED SPERLING

Memory is becoming one of the starting points for SoC architectures, evolving from a basic checklist item that was almost always in the shadow of improving processor performance or lowering the overall power budget. In conjunction with that shift, chipmakers must now grapple with many more front-end decisions about placement, memory type and access prioritization.

Topics: cache coherent IP memory

As Moore’s Law Slows, Hedge Your Bets With Design Process Efficiency

Greater productivity, lower power, smaller die size and greater bandwidth await teams that adopt proven methodologies to streamline design in mature geometries.

Are you dreading the day when Moore’s Law comes to a grinding halt? I’m concerned, but I’m not as fatalistic as some.

Topics: semiconductor industry economics moore's law