Arteris Articles

ADAS Tech Talk Video has 16,000+ views

I just found out from Semiconductor Engineering editor Ed Sperling that the most popular Tech Talk video on semiengineering.com is our Arteris IP 13 minute tutorial on ADAS. The YouTube views are almost 17,000 and Ed has stats that show that people are actually watching most of the video, not just clicking on it and moving on.

I'm glad folks have found it useful!

Topics: ISO 26262 specification semiconductor engineering tech talk video AI training

Semiconductor Engineering: AI Chips: NoC Interconnect IP Solves Three Design Challenges

 Arteris IP's Kurt Shuler warns that regular topologies, large chips, and huge bandwidths are considerations in AI-centric chips in the date center.

AI Chips: NoC Interconnect IP Solves Three Design Challenges  

January 10th,  2019 - By Kurt Shuler

New network-on-chip (NoC) interconnect IP is now available for artificial intelligence (AI) systems-on-chip (SoC). Arteris IP launched the fourth generation of FlexNoC interconnect IP with a new AI package.

The new NoC technology benefits emerging AI chip architectures in three main ways: automatically generating regular topologies, effectively managing the data flows of large chips with long wires and enabling large on- and off-chip bandwidths.

To learn more, please visit the FlexNoC AI Package page; https://www.arteris.com/flexnoc-ai-package and the Resources page: https://www.arteris.com/resources

Topics: semiconductor automotive neural networks AI AI chips flexnoc ai package VC-Links noc interconnect ML AI SoC Designers synchronous virtual channels

SemiWiki: Disturbances in the AI Force

Bernard Murphy (SemiWiki) reflects on a discussion with Kurt Shuler, VP Marketing at Arteris IP, on customer trends in design for advanced ML accelerators, why these look quite different from traditional processor architectures and the implication for design particularly around the NoC interconnect in this SemiWiki blog:

Disturbances in the AI Force

January 3rd, 2019 - By Bernard Murphy

In the normal evolution of specialized hardware IP functions, initial implementations start in academic research or R&D in big semiconductor companies, motivating new ventures specializing in functions of that type, who then either build critical mass to make it as a chip or IP supplier (such as Mobileye - initially) or get sucked into a larger chip or IP supplier (such as Intel or ARM or Synopsys). That was where hardware function ultimately settled, and many still do.

But recently the gravitational pull of mega-companies has distorted this normally straightforward evolution. In cloud services this list includes Amazon, Microsoft, Baidu and others. In smartphones you have Samsung, Huawei and Apple - yep, Huawei is ahead of Apple in smartphone shipments and is gunning to be #1. These companies, neither semiconductor nor IP, are big enough to do whatever they want to grab market share. What they do to further their goals in competition with the other giants can have a major impact on the evolution path for IP suppliers.

Arteris IP is closely involved with many of these companies, from Cambricon to Huawei/HiSilicon to Baidu to emerging companies like Lynxi, offering their network on chip (NoC) solutions with the AI package allowing for architecture tuning to the special needs of high-end NN designs. Check out more here; http://www.arteris.com/flexnoc-ai-package

Topics: NoC semiconductor semiwiki kurt shuler AI chips flexnoc ai package hardware ip accelerators noc interconnect

Semiconductor Engineering: Tech Talk - AI Training Chips Video

Kurt Shuler, VP of Marketing at Arteris IP, chat's about how to speed up algorithms and improve performance:

Tech Talk Video: AI Training Chips 


November 1,  2018 - By Ed Sperling

Ed Sperling interviews Kurt Shuler at Arteris IP headquarters about how to architect an AI training chip.

Arteris IP’s Kurt Shuler provides details about how different processing elements are used to accelerate training algorithms, and how to achieve improved performance .
Topics: semiconductor IoT automotive neural networks AI tech talk video algorithms AI chips AI training data centers

New Resources page on Arteris IP website (www.arteris.com/resources)

We've had a lot of requests for easier access to Arteris IP downloads and other online resources like product datasheets, technical papers, event presentations and proceedings, videos and newspaper articles. To help with this, I've created a resources page at http://www.arteris.com/resources.

Topics: arteris ip

Semiconductor Engineering: What Makes A Good Accelerator

Kurt Shuler, VP of Marketing at Arteris IP, comments on 'What needs to be accelerated' in this Semiconductor Engineering article:

What Makes A Good Accelerator

 

October 25th, 2018 - By Ann Steffora Mutschler

Topics: FPGAs machine learning neural network semiconductor engineering soc architecture arteris ip SoCs