Arteris Articles

SemiWiki: Safety: Big Opportunity, A Long and Hard Road

Kurt Shuler, VP Marketing at Arteris IP, explains the support and business cycle from the vendor to the integrator in the latest SemiWiki blog written by Bernard Murphy:

Safety: Big Opportunity, A Long and Hard Road

February 27th, 2019 - By Bernard Murphy

Still think you want to sell IP into the automotive chain? Bernard Murphy (SemiWiki) distills Kurt Shuler insights into what this takes. There’s certainly a lot of promise. More big chips in the central brain and in intelligent sensors together offer a lot of opportunity. The US, Europe and Israel markets are all very aggressive in developing ADAS and ML. China has been a laggard but is coming on strong and is not held back by legacy so much. They also see a big tie-in with AI where they are very strong. Kurt says there are more than a couple of hundred funded startups in automotive and AI in China.

That said, this is not an easy way to get rich. You’ll have to put a lot of investment into supporting your customers, supporting their customers and so on up to the top. The market is very dynamic, so what “done” means may not always be clear. You may not be paid for quite a long time. But if you have the grit to hang on and keep your customer happy the whole way through, you might just be successful!


 For more information, download this FlexNoC AI Package datasheet; http://www.arteris.com/flexnoc-ai-package

Topics: ISO 26262 semiconductor semiwiki kurt shuler flexnoc ai package noc interconnect ML-centric design

Semiconductor Engineering: Using AI Data For Security

 Arteris IP's Kurt Shuler, Vice President of Marketing, comments about the edge emerging as a particular security concern because some of the devices can kill you, covered in this Semiconductor Engineering article;

Using AI Data For Security

February 20th, 2019 - By Ann Steffora Mutschler

Pushing data processing to the edge has opened up new security risks, and lots of new opportunities. 

The edge and beyond
“It’s cars and robots and medical devices,” said Kurt Shuler, vice president of marketing at Arteris IP. “These things can kill you two ways. A cosmic ray can cause a bit to flip, and things go awry. The other way is that the AI may work as intended, but what it decides to do from its neural net application is the wrong thing. In that case, the safety of the intended function is bad.”

There’s even a new spec just for this: “ISO/PAS 21448:2019 Road vehicles — Safety of the intended functionality.” That captures how to analyze these AI powered systems going into cars, so they works as designed.

Security can impact all of these systems. “There’s a totally separate set of specs, and a totally separate set of Ph.D. geeks working on safety and on security,” said Shuler. “What’s disconcerting is that the effects of any of these things, especially from a functional safety standpoint and a security standpoint, can be the same. Whether a bit flips or an engineer flipped a bit, someone can get hurt. Yet these sets of experts don’t really talk to each other too much. This was addressed in the new ISO 26262 2018 specification that came out in December, which includes specific text to address this. It basically says you must coordinate with security guys, but unless security is somehow mandated to a certain level — like functional safety is in cars and trains and other verticals — nobody really cares. It’s like insurance. Nobody wants to pay for too much security.”

For more information about ISO 26262:2018 Part 11, please download this presentation "Fundamentals of ISO 26262 Part 11 for Semiconductors".

Topics: semiconductor automotive AI ISO PAS 21448 data centers noc interconnect ML AI SoC Designers ecosystem

EE Times article, IoT Was Interesting, But Follow the Money to AI Chips

Kurt Shuler, VP Marketing at Arteris IP, states that the upcoming change in focus will be so radical, that by 2025, a full five sixths of the growth in semiconductors is going to be the result of AI. 

February 2, 2019 - by Kurt Shuler

A few years ago there was a lot of buzz about IoT, and indeed it continues to serve a role, but looking out to 2025 the real dollar growth for the semiconductor industry is in algorithm-specific ASICs, ASSPs, SoCs, and accelerators for Artificial Intelligence (AI), from the data center to the edge.

Anyone tracking the industry closely knows how we got to this point. Designers were implementing IoT before it even became a “thing.” Deploying sensors and communicating on a machine-to-machine level to perform data analysis and implement functions based on structural or ambient environment and other parameters just seemed like a smart thing to do. The Internet just helped to do it remotely. Then someone latched onto the term “the Internet of things” and suddenly everyone’s an IoT silicon, software, or systems player.

Topics: semiconductor eetimes autonomous vehicles AI automotive design SoCs kurt shuler training data centers edge 28 nm

Semiconductor Engineering: The Race To Multi-Domain SoCs

 Arteris IP's CEO looks at how automotive and AI are Altering chip design in this article in Semiconductor Engineering;

The Race To Multi-Domain SoCs

February 7th,  2019 - By Ed Sperling

K. Charles Janac, president and CEO of Arteris IP, sat
down with Semiconductor Engineering to discuss the impact of automotive and AI on chip design. What follows are excerpts of that conversation.

SE: What do you see as the biggest changes over the next 12 to 24 months?
Janac: There are segments of the semiconductor market that are shrinking, such as DTV and simple IoT. Others are going through an investment phase, including automotive, AI/machine learning and China. You really want to be focused on those segments. 

SE: So does IP that’s being developed today look radically different than it did five years ago?
Janac:
Yes, everything is getting amazingly complex. What people are building right now are multi-domain SoCs. The CPU, which used to do all the work, does relatively less work. There are accelerators for vision and data analysis outside of the CPU subsystem. There are machine learning sections, some general-purpose, some very specific, all on-chip. There is a memory subsystem with very high-bandwidth memory and low latency. There also is functional safety. You need tremendous performance because a car is a supercomputer on wheels. The car has to be very efficient, because you need to deliver that compute power without water cooling. Power management becomes very sophisticated. And then there are functional safety and security subsystems to keep these safe from environmental and man-made issues.

SE: Where does the network on chip (NoC) fit into all of this?
Janac: All data goes through the NoC of the chip. There are opportunities for generating value from that. But the increase in complexity is increasing the number and sophistication of the interconnect parts of the chip. Before, you may have had networks on chip. Now you may have 20 or 30.

Topics: semiconductor automotive ADAS neural networks AI LIDAR flexnoc ai package noc interconnect ML AI SoC Designers chiplets

Semiconductor Engineering: ISO 26262:2018, 2nd Edition: What Changes?

 Arteris IP's Kurt Shuler, vice president of marketing, delivers a recent update for the ISO 26262 standard in this blog in Semiconductor Engineering;

ISO 26262:2018, 2nd Edition: What changes?

February 7th,  2019 - By Kurt Shuler

The safety standard is now clearer for IP-based designs and those happening across multiple companies.

If you’re involved somehow in design for automotive electronics, you probably have more than a cursory understanding of the ISO 26262 standard. What your organization is working from is most likely the 2011 definition. The most recent update is formally known as ISO 26262:2018, less formally as ISO 26262 2nd Edition.

Standards should evolve, but what changed and why? I’ve been a member of the ISO 26262 working group for many years, and particularly involved in how it should be interpreted for IP, and I’ve got to tell you, I have struggled. 

From my perspective, it was originally written around an implicit expectation that chips are built from scratch entirely within one organization, and this is a dated assumption. There was also not enough guidance for IP-based design or design distributed across multiple companies or sites. The workaround for an IP supplier has been to use the Safety Element out of Context (SEooC) mechanism. But this depends heavily on human interpretation, by the component vendor on what may be relevant to the integrator and vice-versa, with little guidance from the 2011 version of the standard. I complained (whined?) quite a bit to the committee about these problems and they eventually invited me to the working group. I wasn’t the only one confused and other people joined, and we seem to have had an impact; our efforts have resulted in a lot more clarification, organization and practical examples in the latest standard. I think the new Part 11 of the updated standard provides a lot more detail and useful examples for us in the semiconductor and semiconductor IP industry.

For more information about ISO 26262:2018 Part 11, download the 39-slide Arm TechCon presentation titled, “Fundamentals of ISO 26262 Part 11 for Semiconductors,” by Arteris IP Functional Safety Manager Alexis Boutillier and ResilTech Scientific Advisor Dr. Andrea Bondavalli, or watch my very popular SemiEngineering “Tech Talk: ISO 26262 Drilldown” video.

Topics: semiconductor automotive neural networks ISO 26262 certification AI AI chips flexnoc ai package noc interconnect ML AI SoC Designers

Arteris IP at DVCon 2019 Silicon Valley

Arteris IP at DVCon U.S. 2019 

Location: DoubleTree Hotel, 2050 Gateway Place, San Jose, CA
Poster Sessions: Tuesday, 26 February, 10:30am - 12:00pm, Gateway Foyer, 2nd level

Arteris IP is presenting the poster, "4.8 Flex-Checker: A One Stop Shop for all your Checkers: A Methodology for Elastic Score-boarding"

Topics: NoC hardware verification semiconductor latency bandwidth SoCs performance noc interconnect

SemiWiki: Why High-End ML Hardware Goes Custom

Kurt Shuler, VP Marketing at Arteris IP,  provides more insight into what's happening in this highly dynamic space in the latest SemiWiki blog written by Bernard Murphy (SemiWiki):

Why High-End ML Hardware Goes Custom

January 30th, 2019 - By Bernard Murphy

In a hand-waving way it’s easy to answer why any hardware goes custom (ASIC): faster, lower power, more opportunity for differentiation, sometimes cost though price isn’t always a primary factor. But I wanted to do a bit better than hand-waving, especially because these ML hardware architectures can become pretty exotic, so I talked to Kurt Shuler, VP Marketing at Arteris IP, and I found a useful MIT tutorial paper on arXiv. Between these two sources, I think I have a better idea now.

Start with the ground reality. Arteris IP has a bunch of named customers doing ML-centric design, including for example Mobileye, Baidu, HiSilicon and NXP. Since they supply network on chip (NoC) solutions to those customers, they have to get some insight into the AI architectures that are being built today, particularly where those architectures are pushing the envelope. What they see and how they respond in their products is revealing.

You can learn more about what Arteris IP is doing to support AI in these leading-edge ML design teams HERE. They certainly seem to be in a pretty unique position in this area.

 For more information, download this FlexNoC AI Package datasheet; http://www.arteris.com/flexnoc-ai-package

Topics: NoC semiconductor semiwiki kurt shuler AI chips flexnoc ai package accelerators noc interconnect ML-centric design

Semiconductor Engineering: Chasing Reliability In Automotive Electronics

 Arteris IP's Kurt Shuler, vice president of marketing has authored a paper about ISO 26262 and comments in this article;

Chasing Reliability In Automotive Electronics 

January 15th,  2019 - By Susan Rambo and Ed Sperling

Supply chain changes, resistance to sharing data and technology unknowns add up to continued uncertainty.

"Traditional semiconductor vendors who are making or designing chips to enable autonomous driving applications are nowadays sometimes competing with Tier-1 electronics system designers and OEMs, who may be making their own chips or providing explicit requirements to their semiconductor vendor partners. Additionally, new entrants like Uber, Way and Apple are designing their own complete systems, despite their relative lack of experience in the automotive industry. ISO 26262 mandates high levels of collaboration and information sharing throughout the value chain that may be unfamiliar to new entrants."

The ISO 26262 standard is snapshot of issues and the lengths the whole supply chain has to go. Collaboration is key. Communication is part of the safety standards up and down the automotive safety critical supply chain now. It’s built into the standards.

Sharing knowledge of a supplier’s crown jewels—intellectual property—has to happen among suppliers and auto OEMs. “Participants in the semiconductor and software supply chains are usually secretive about how their IP was developed and how it works in detail,” said Shuler. Suppliers should remember that the “your customer still has an obligation to confirm your compliance with ISO 26262.”

To learn more, please download this technical paper, Fundamentals of Semiconductor ISO 26262 Certification: People, Process and Product.

Topics: semiconductor automotive neural networks ISO 26262 certification AI AI chips flexnoc ai package noc interconnect ML AI SoC Designers