Arteris Articles

Arteris IP is Hiring a Senior Software Engineering Manager in Campbell, CA!

Featured Position!

Senior Software Engineering Manager in Campbell, CA

Would you like to be part of a team contributing to products that will be used in the next-generation of advanced smartphones, automobiles and other computing devices?

This management position reporting to the VP of Engineering requires a dynamic and self-motivated individual with excellent organizational, and technical skills who can effectively communicate across all levels of management. The ideal candidate will be an experienced leader who is visionary, strategic, technology savvy and skilled in contemporary software technologies and architectures. You will own and drive both development and quality engineering across multiple development teams.

Topics: software jobs arteris ip noc interconnect job SoC designs C++ Java leader IP design EDA

SystemC Gurus Wanted! Arteris IP is Hiring Performance Modeling Engineers

Featured Position!

Performance Modeling Engineer
in Campbell, CA or Austin, TX

Would you like to be part of a team contributing to products that will be used in the next-generation of advanced smartphones, automobiles and other computing devices?

Topics: AXI OCP ASIC design cache coherency system level modeling SystemC arteris ip SoCs noc interconnect job

Arteris IP is Hiring a Software Architect in Campbell, CA

Featured Position!

Software Architect

We are looking for an experienced Software Architect to participate in the architecture and design of its next generation network-on-chip (NoC) interconnect design and optimization software.

Our current product is powering the creation of the most advanced artificial intelligence, mobile phone, and self-driving car SoCs.

Topics: software jobs arteris ip noc interconnect job SoC designs C++ Java

Arteris IP perspective on EE Times, "Facebook Buys Interconnect IP Vendor Sonics"

Junko Yoshida from EE Times wrote an insightful article titled, "Facebook Buys Interconnect IP Vendor Sonics," that does a really good job explaining the changes in the semiconductor industry and exploring why big companies like Intel and Facebook are buying interconnect IP companies. 

Topics: acquisitions semiconductor eetimes autonomous vehicles AI SoCs facebook sonics intel

SemiWiki: Segmenting the Machine-Learning Hardware Market

Kurt Shuler, VP Marketing at Arteris IP, shares his 91 entries into finding every company and product that is active in the AI hardware space in this latest SemiWiki blog:

Segmenting the Machine-Learning Hardware Market

March 13th, 2019 - By Bernard Murphy

Machine learning is everywhere, but it can be difficult at times to understand what that really means. Bernard Murphy (SemiWiki) talked to Kurt Shuler and dug through a very detailed spreadsheet Kurt developed to understand better better what is being used where in the ML market.

One of the great pleasures in what I do is to work with people who are working with people in some of the hottest design areas today. A second-level indirect to be sure but that gives me the luxury of taking a broad view. A recent discussion I had with Kurt Shuler (VP Marketing at Arteris IP) is in this class. As a conscientious marketing guy, he wants to understand the available market in AI hardware because they have quite a bit of activity in that space – more on that later. So Kurt put a lot of work into finding every company and product he could that is active in this space, 91 entries in his spreadsheet. This he broke down by company, territory (eg China or US), product, target market (eg vision or speech), implementation (eg FPGA or ASIC), whether the product is used in datacenters or at the edge and whether it is being used for training or inference. 


 For more information, download this FlexNoC AI Package datasheet; http://www.arteris.com/flexnoc-ai-package

Topics: FPGA semiconductor edge computing semiwiki inference kurt shuler flexnoc ai package AI training noc interconnect

Arteris IP is Hiring a Senior Hardware Verification Engineer in Austin, TX!

Featured Position!

Senior Hardware Verification Engineer
for our Austin, TX Office

Do you want to contribute to the backbone of the some of the world's most popular SoCs?

You will create designs in a powerful language that blends traditional RTL with leading-edge software to provide extremely configurable, testable, and high-quality solutions. You’ll go home at the end of the day amazed at all the places where your creations end up. 

Topics: arteris ip hardware RTL noc interconnect job SoC designs Verilog

Arteris IP at DATE 2019

Arteris IP at DATE 2019 

Location: Firenze Fiera, Florence, Italy
3.1 Executive Session 2: Panel
Date:
Tuesday, 26 March 2019
Time: 14:30 - 16:00
Location: Room 1

Arteris IP's CEO, K. Charles Janac joins this Executive Panel Session, "Semiconductor IP, Surfing the Next Big Wave"

Topics: FPGA semiconductor Soft IP SoCs noc interconnect hard ip

Arteris IP is Hiring!

Performance Modeling Engineer
in Campbell, CA or Austin, TX

Would you like to be part of a team contributing to products that will be used in the next-generation of advanced smartphones, automobiles and other computing devices?

Topics: AXI OCP ASIC design cache coherency arteris ip hardware SoCs noc interconnect job

Semiconductor Engineering: How To Build An Automotive Chip

 Arteris IP's Kurt Shuler, Vice President of Marketing, comments about the claims of technical safety requirements in this Semiconductor Engineering article;

How To Build An Automotive Chip

March 7th, 2019 - By Ann Steffora Mutschler

Changing standards, stringent requirements and a mix of expertise make this a tough marketing to crack.

IP issues
“One of the things that all of these guys deal with is having evidence that the specifications are being followed, both from a process standpoint of how the IP is designed,” said Kurt Shuler, vice president of marketing at Arteris IP. “And then, does the IP meet the technical safety requirements that are being claimed?”

This requires the IP customer to look closely at their different IP providers. “If I’m licensing some IP, I want to understand in pre-sales what do you have, how did you build it,” said Shuler. “What evidence and work products do you have to prove any claims that you make? Things may go quiet for a while until the design team gets closer to the end of the chip design project and starts doing the work where they have to calculate the diagnostic coverage and FMEDA, maybe some fault injection to validate, some of the assumptions they make in the FMEDA, among other activities.”

“If our customer or prospect has somebody who doesn’t understand functional safety or the specification, and is just going blindly through a checklist, it slows things down,” Shuler said. “So the right subject matter experts must be there.”

For more information about ISO 26262:2018 Part 11, please download this presentation "Fundamentals of ISO 26262 Part 11 for Semiconductors".

Topics: SoC functional safety ISO 26262 automotive semiconductor engineering AI RTL noc interconnect ML/AI

EE Times article, "AV Safety Ventures Beyond ISO 26262"

Kurt Shuler, VP Marketing at Arteris IP, was interviewed and quoted in this interesting article on the new SOTIF ISO/PAS 21448:2019 specification. 

March 5, 2019 - by Junko Yoshida

Close vote
Kurt Shuler, vice president of marketing at Arteris, said that it was a “close vote” at the ISO 26262 meeting when the group decided to develop SOTIF as a separate standard. Skeptics questioned the need, he noted. Citing “known unknowns” and “unknown unknowns,” Shuler acknowledged, “We are getting into the realm of Donald Rumsfeld,” the former United States Secretary of Defense.

Topics: semiconductor eetimes autonomous vehicles ISO 26262 specification AI automotive design SoCs kurt shuler edge

Arteris IP at Synopsys Users Group Silicon Valley 2019


Arteris IP at SNUG Silicon Valley 2019 

Location: Santa Clara Convention Center, 5001 Great America Parkway, Santa Clara, CA  
Track: Artificial Intelligence - Wednesday, 20 March, 3:45 pm - 4:30 pm

Arteris IP is presenting this paper, "Using Machine Learning for Characterization of NoC Components"

Topics: NoC semiconductor FlexNoC Soft IP SoCs RTL noc interconnect ML PPA