Arteris Articles

SemiWiki: ML and Memories: A Complex Relationship

Kurt Shuler, VP Marketing at Arteris IP, helped Bernard Murphy (SemiWiki) learn the multiple ways that different types of memory need to connect to these accelerators in the latest SemiWiki blog:

ML and Memories: A Complex Relationship

March 13th, 2019 - By Bernard Murphy

How do AI architectures connect with memories? The answer is more complex than in conventional SoC architectures.

No, I’m not going to talk about in in-memory-compute architectures. There’s interesting work being done there but here I’m going to talk here about mainstream architectures for memory support in Machine Learning (ML) designs. These are still based on conventional memory components/IP such as cache, register files, SRAM and various flavors of off-chip memory, including not yet “conventional” high-bandwidth memory (HBM). However, the way these memories are organized, connected and located can vary quite significantly between ML applications.

For more information, please visit the Arteris IP AI package webpage: http://www.arteris.com/flexnoc-ai-package

Topics: semiconductor artificial intelligence semiwiki kurt shuler flexnoc ai package noc interconnect cache coherence

Semiconductor Engineering: The Long and Detailed Road to Automotive Compliance

 Arteris IP's Kurt Shuler, Vice President of Marketing, comments in the latest Semiconductor Engineering article.

The Long and Detailed Road to Automotive Compliance

April 4th, 2019 - By Ann Steffora Mutschler

Bringing an engineering organization up to speed with automotive safety standards is a long and arduous process. 

Complexity on complexity
Things can get complicated very fast. Kurt Shuler, vice president of marketing at Arteris IP, said it is not uncommon in SOTIF applications to hear, “‘I’m going to do a system and it’s got cameras, and it’s got radars, and the radars have cameras, and there are sensors.’ It’s very complicated. People ask us how to protect against this and that, and how to ensure this thing works and what can be done in the interconnect to help with that. So we get pulled into these really high-level questions. And because an interconnect is configurable IP, and each customer’s design is totally different, we also get pulled into discussions around the process aspect to ISO 26262 when using configurable IP as opposed to a hard macro. These companies are asking us 1,001 questions about that, and it really is difficult. What we generally have to do is agree upfront that we are responsible for a specific part of the specification. And as a safety element out of context, we are responsible for this type of analysis and this kind of stuff; here are our assumptions of use and everything; and we agree on this. Any other insights we give to them is something we do to help them, but it’s not necessarily part of a contract or that’s required. The reason to have that agreement up front is because a lot of these companies are new to automotive, and we have a lot of experience, but we don’t want to be an ISO 26262 consultancy.”

For more information, please click and download this presentation; ISO 26262: What to expect from your chip or IP provider: https://www.arteris.com/download-iso-26262-what-to-expect-from-your-chip-or-ip-provider

Topics: SoC ISO 26262 automotive semiconductor engineering noc interconnect SOTIF (ISO 21448

Semiconductor Engineering: Racing To The Edge

 Arteris IP's Kurt Shuler, Vice President of Marketing, comments in the latest Semiconductor Engineering article.

Racing To The Edge

April 9th, 2019 - By Susan Rambo and Ed Sperling

The race is on to win a piece of the edge despite the fact that there is no consistent definition of where the edge begins and ends or how the various pieces will be integrated or ultimately tested.

Safety lives at the edge
“The edge includes a lot of the stuff where people are most concerned about things that can kill you, like cars and robots and medical devices,” said Kurt Shuler, vice president of Arteris IP. “These things can kill you two ways. One is a cosmic ray and the traditional functional safety use case, where it flips a bit and then it goes awry. The other way is everything works as intended, however what it does and what it decides to do from its neural net application is the wrong thing. There’s not a cosmic ray. There’s not a hardware safety problem. The safety of the intended function is bad. (There is a new specification out for that, ISO/PAS 21448:2019 Road Vehicles — Safety of the Intended Functionality.)”

For more information on AI, please click on the Arteris FlexNoC AI Package webpage: http://www.arteris.com/flexnoc-ai-package.

Topics: SoC ARM automotive semiconductor engineering safety noc interconnect edge ISO/PAS Intended functionality

Arteris IP is Hiring a Hardware Verification Engineer in Paris!

Featured Position!

Hardware Verification Engineer in Paris (Guyancourt), France

Do you want to contribute to the backbone of the some of the world's most popular SoCs? You will work with an expert team to design and deliver interconnect & memory hierarchy solutions. You'll verify designs created in a powerful language that blends traditional RTL with leading-edge software to provide extremely configurable, testable, and high-quality solutions. You’ll have to ensure that our IPs are matching the specifications before been released to our customers, to be part of a SoC for AI, IoT, automotive, mobile... our IP is used everywhere!

Topics: hardware verification arteris ip RTL noc interconnect job SoC designs C/C++ Python

Arteris IP Awarded 1st Place for Technical Paper at Synopsys Users Group (SNUG) Silicon Valley 2019

Benny Winefeld, Solutions Architect at Arteris IP, Awarded 1st Place Best Paper Award at SNUG Silicon Valley 2019 

Arteris IP presented this technical paper, "Using Machine Learning for Characterization of NoC Components", on March 20, 2019.

Benny Winefeld, Solutions Architect at Arteris IP, accepted the 1st Place Best Paper Award from the SNUG Technical Committee during SNUG Silicon Valley. There were 29 papers that competed for the best paper award.

In the photo above, Benny receives the award from the SNUG committee, from left to right: Ken Nelson, VP Field Support Operations; Benny Winefeld, Solutions Architect, Arteris IP; Tony Todesco, SNUG SV Technical Chair, AMD; and Deirdre Hanford, Co-GM, Synopsys.

Topics: Synopsys NoC machine learning artificial intelligence Soft IP noc interconnect SNUG

Semiconductor Engineering: Big Shift In Multi-Core Design

 Arteris IP's Kurt Shuler, Vice President of Marketing, adds commentary in this article in Semiconductor Engineering.

Big Shift In Multi-Core Design

April 3rd, 2019 - By Ann Steffora Mutschler

System-wide concerns in AI and automotive are forcing hardware and software teams to work together, but gaps still remain.

Minding the gap
There are indications that mindset is beginning to change, particularly in markets such as automotive where systemic complexity extends well beyond a single chip or even a single vehicle.

“In the past, if you were a software engineer, the thinking was, ‘I have this chip available. Here’s what I can produce with my software,'” said Kurt Shuler, vice president of marketing at Arteris IP. “Nowadays, especially in the ADAS side of things that have an AI component or some kind of programmable object detection for the ADAS functionality, or an AI chip—whether it’s for the data center, edge, inference or training—the thinking has shifted more to system-design decisions. If this is designed with this given set of software algorithms, it is clear what needs to happen at a system level from the hardware and software point of view. At what level of detail should I optimize this hardware for the particular software I expect to run? This means the hardware and the software are now much more tightly integrated in those use cases than they probably have ever been unless it’s a very detailed embedded application. So now, in the early stages of design for these types of chips, whether it’s the autonomous driving chips or the AI chips, the software architect is in there, too.”

This is a definite sign of progress. “Before, they didn’t care,” Shuler said. “The layer/API between hardware and software is becoming less generic and more specific for those kinds of use cases, solving those kinds of problems. What that means, though, is there are software guys who went to Stanford and trained on Java script and have no idea what a register is. Then there are hardware guys who have no idea what a hypervisor or object-oriented programming is.”

For more information on AI, please click on the Arteris FlexNoC AI Package webpage: http://www.arteris.com/flexnoc-ai-package.

Topics: SoC software automotive ADAS autonomous driving semiconductor engineering AI hardware noc interconnect

Arteris IP is Presenting at The Linley Spring Processor Conference April 10 - 11, 2019!


Don't Miss the Arteris IP Presentation on AI SoC Architectures, Thursday, April 11, 2019 

Location: Hyatt Regency, Santa Clara, CA
Session 5: SoC Design: Thursday, April 11
1:15 pm - 2:45 pm

Arteris IP presenting: "Adapting SoC Architectures for Types of Artificial-Intelligence Processing"

Come to the Linley Spring Processor Conference on April 10 - 11, 2019  - and attend the Arteris IP presentation on Thursday, April 11 during Session 5: SoC Design, were we will describe lessons learned on how to use network-on-chip (NoC) technology to efficiently implement SoC architectures targeted for different types of AI processing, including advanced techniques like when to use tiling or cache coherence, whether for edge/battery-operated or datacenter chips. 

April 11 Agenda: https://www.linleygroup.com/events/agenda.php?num=46&day=2

Topics: NoC semiconductor ArterisIP artificial intelligence SoCs edge/battery-operated cache coherence datacenter chips