Arteris Articles

New! Arteris IP Technical Paper, Re-Architecting SoCs for the AI Era

Kurt Shuler, VP of Marketing at Arteris IP has written this 10-page technical paper titled, "Re-Architecting SoCs for the AI Era".

August 29, 2019 - by Kurt Shuler

Abstract:
The growth of artificial intelligence (AI) demands that semiconductor companies re-architect their system on chip (SoC) designs to provide more scalable levels of performance, flexibility, efficiency, and integration. From the edge to data centers, AI applications require a rethink of memory structures, the numbers and types of heterogeneous processors and hardware accelerators, and careful consideration of how the dataflow is enabled and managed between the various high-performance IP blocks.

Topics: functional safety ISO 26262 semiconductor machine learning autonomous driving artificial intelligence AI SoCs kurt shuler noc interconnect ML dataflow

EE Times article, The Gatekeeper of a Successful Design is the Interconnect

K. Charles Janac, President and CEO, at Arteris IP, authored this article on how an effective interconnect makes delivering a complex SoC easier, more predictable, and less costly.

August 25, 2019 - by K. Charles Janac

An interconnect handles various types of traffic inside an SoC and is a mechanism for effective IP block integration. The interconnect is the most configurable IP in the SoC — typically changing many times during a project and nearly always changing between projects. It also plays a vital role in security and functional safety because it carries most of the SoC data and contains nearly all the SoC’s long wires and system-level services, including quality of service (QoS), visibility, physical awareness, and power management. The interconnect enables cache coherency in multiprocessor SoCs, high-performance and bandwidth levels in advanced driver assistance systems (ADAS) automotive chips and networking SoCs, and ultra-low power in long-running consumer devices.

Topics: semiconductor eetimes advanced driver assistance systems adas autonomous driving AI K. Charles Janac SoCs noc interconnect ML data center automation

Semiconductor Engineering: Chiplets, Faster Interconnects, More Efficiency

 Arteris IP's K. Charles Janac, president and CEO, chats with Ed Sperling at Hot Chips in this latest Semiconductor Engineering article:

Chiplets, Faster Interconnects, More Efficiency

August 22nd, 2019 - By Ed Sperling

Big chipmakers are turning to architectural improvements such as chipsets, faster throughput both on-chip and off-chip, and concentrating more work per operation or cycle, in order to ramp up processing speeds and efficiency.

 

“Everyone is struggling with CCIX,” said K. Charles Janac, president and CEO of Arteris IP. “If you have an accelerator and two coherent dies, there are too many corner cases to get it to work easily. But now you can use 3D interconnects to hook together a planar CPU and a planar I/O. So this looks like one system to the software, and you have inter-chip links between the network on chip and different die. That way you can support non-coherent and coherent read/write across two die. It makes the interconnect more valuable, but it also makes it more complicated.”

“The memory controller and the NoC will have to be much more tightly integrated,” said Janac. “The problem is that neither one understands the QoS of the entire chip, and there aren’t any independent memory controller companies left. But memory traffic has to be better integrated to make this work.”

For more information, please visit our Resources page for free downloads of our technical papers; http://www.arteris.com/resources

Topics: SoC ArterisIP FlexNoC ncore cache coherent interconnect semiconductor engineering K. Charles Janac noc interconnect Hot Chips

Semiconductor Engineering: Where Should Auto Sensor Data Be Processed?

 Arteris IP's Kurt Shuler, Vice President of Marketing, comments in this latest Semiconductor Engineering article:

Where Should Auto Sensor Data Be Processed?

August 1st, 2019 - By Ann Steffora Mutschler

Fully autonomous vehicles are coming, but not as quickly as the initial hype would suggest...

 

Indeed, when it comes to processing the sensor data, a number of approaches currently point to allowing for scaling between different ADAS levels, but which the best way to do that is still up for debate.

“There must be an architecture they can do that with, and the question is, ‘How do you do that?'” said Kurt Shuler, vice president of marketing at Arteris IP. “There’s a lot of interest in getting more hardware accelerators to manage the communications in software, and directly managing the memory. For this, cache coherence is growing in importance. But how do you scale a cache coherent system? This must be done in an organized way, as well as adding a whole bunch of masters and slaves to it, such as additional clusters.”

For more information, please download the Arteris FlexNoC Interconnect IP data sheet; https://www.arteris.com/download-flexnoc-datasheet

Topics: SoC autonomous driving ArterisIP FlexNoC semiconductor engineering LIDAR noc interconnect cache coherence hardware accelerators