Arteris Articles

SemiWiki: AI, Safety and Low Power, Compounding Complexity

Bernard Murphy talked to Kurt Shuler about the complexities of combining low power, safety and AI constraints in a design. Design challenges have evolved beyond PPA to encompass new constraints but these are still manageable, with the right architecture in this new SemiWiki blog:

AI, Safety and Low Power, Compounding Complexity 

April 28th, 2020 - By Bernard Murphy

The nexus of complexity in SoC design these days has to be in automotive ADAS devices. Arteris IP highlighted this in the Linley Processor Conference recently where they talked about an ADAS chip that Toshiba had built. This has multiple vision and AI accelerators, both DSP and DNN-based. It is clearly aiming for ISO 26262 ASIL D certification since the design separates a safety island from the processing island, pretty much the only way you can get to ASIL D in a heterogenous mix of ASIL-level on-chip subsystems. Equally clear, it’s aiming to run at low power – around 2.7W for the processing island (the bulk of the functionality). It’s all very well to be smart but when you have dozens of smart components scattered around the car, that adds up to a lot of power consumption. The car isn’t going to be very smart if it runs its battery flat.

 

Topics: SoC ISO 26262 semiconductor Toshiba ADAS Ncore FlexNoC AI semiwiki ASIL D noc interconnect memory hierarchy

SemiWiki: That Last Level Cache is Pretty Important

Bernard Murphy talked to Kurt Shuler to get an update on the Arteris IP CodaCache IP. That led to some insights not just on what has changed but also why last level cache is so important in this new SemiWiki blog:

That Last Level Cache is Pretty Important

April 21st, 2020 - By Bernard Murphy

Last-level cache seemed to me like one of those, yeah I get it, but sort of obscure technical corners that only uber-geek cache specialists would care about. Then I stumbled on an AnandTech review on the iPhone 11 Pro and Max and started to understand that this contributes to more than just engineering satisfaction.

For more information, please download this paper: https://www.arteris.com/download-technical-paper-codacache-helping-to-break-the-memory-wall

Topics: SoC ISO 26262 semiconductor ArterisIP AI semiwiki last level cache kurt shuler noc interconnect memory hierarchy Coda Cache LLC

Arteris IP is HIRING...BIG TIME!

Even though we're all doing social distancing, Arteris IP is actively hiring!

Topics: software jobs hardware jobs arteris jobs hiring

Semiconductor Engineering: Last-Level Cache Video

Tech Talk Video: Last-Level Cache 

April 6th, 2020 - By Ed Sperling

Kurt Shuler, vice president of marketing at Arteris IP, explains how to reduce latency and improve performance with last-level cache in order to avoid sending large amounts of data to external memory, and how to ensure quality of service on a chip by taking into account contention for resources.

Topics: network-on-chip semiconductor CodaCache tech talk video on-chip memory data centers memory hierarchy semiengineering

Semiconductor Engineering: Tracking Automotive's Rapidly Shifting Ecosystem

Kurt Shuler, vice president of marketing at Arteris IP is quoted in this Semiconductor Engineering article:

Tracking Automotive's Rapidly Shifting Ecosystem

April 2nd, 2020 - By Ann Steffora Mutschler

 Arteris IP, which has been active in the automotive market since 2010 and has established relationships with most of the automotive semiconductor players, this behavior is not a surprise.
 
“There’s paperwork that goes back and forth about who has been certified for what, or how to go about assessments or about ISO 26262,” said Kurt Shuler, vice president of marketing at Arteris IP. “For companies new to this, whether on the semiconductor side making an automotive chip or an IP that’s going into automotive, it can be weird to get questions from customers asking for the processes to be described, or how traceability of requirements is done through to the specifications, and the implementation queue. If you’re not in automotive or medical devices or something similar, like military/aerospace, you’re not used to being asked those questions or even revealing that information externally. If you’re new to an automotive chip, or new to automotive IP, you have to deal with that. It’s an education process.”
 
Topics: SoC ISO 26262 automotive ADAS autonomous vehicles NoC technology semiconductor engineering OEMs noc interconnect Tier 1s IP market

Semiconductor Engineering: AI, Performance, Power, Safety Shine Spotlight on Last-Level Cache

Kurt Shuler, vice president of marketing at Arteris IP writes about overcoming memory limitations in automotive systems in this Semiconductor Engineering article:

AI, Performance, Power, Safety Shine Spotlight on Last-Level Cache

April 2nd, 2020 - By Kurt Shuler

Memory limitations to performance, always important in modern systems, have become an especially significant concern in automotive safety-critical applications making use of AI methods. On one hand, detecting and reporting a potential collision or other safety problem has to be very fast. Any corrective action is constrained by physics and has to be taken well in advance to avoid the problem.
 
Topics: SoC automotive NoC technology semiconductor engineering CodaCache performance last level cache noc interconnect IP market

Arteris IP is Now Hiring a Corporate Application Engineer in Campbell, CA

This is a New Position!

Corporate Application Engineer in Campbell, CA

Now is the time to join Arteris IP!

Do you want to contribute to the backbone of some of the world’s most popular SoCs?

As a Corporate Application Engineer at Arteris, you will work with an expert team to support and deploy interconnect and memory hierarchy solutions for some of the world’s most sophisticated mobile, telecom, automotive, AI and consumer SoC designs.

Topics: software jobs functional safety ISO 26262 arteris ip noc interconnect job SoC designs leader IP design