Holger Keding (Synopsys' Solutions Architect), Rocco Jonack (Arteris' Senior Solutions Architect) and Malte Doerper (Synopsys' Product Marketing) will be jointly hosting this webinar,
"Optimization of Cache Coherent Interconnects for Artificial Intelligence SoCs",
on Wednesday, 26 September, at 10 am Pacific time.
This webinar will review the challenges associated with cache-coherent interconnect optimization and the benefits of early analysis using virtual prototypes. An embedded vision case study will be presented featuring Synopsys Platform Architect Ultra and Arteris Ncore Cache Coherent Interconnect IP, that also features a fast and Platform Architect compliant simulation model.
The case study will be used to illustrate how architects can:
- Assemble a virtual architecture model of an SoC that contains coherent and non-coherent processing elements and cache-coherent interconnect.
- Create and use application workload models, that can be mapped to virtual architecture models.
- Simulate the workload and architecture model to measure, analyze, and explore the impact that application mapping and cache-coherent interconnect and memory subsystem configuration have on performance and power to optimize the system.
This webinar is intended for system designers, SoC architects, hardware engineers, and project managers involved in the development of cache-coherent architectures for heterogeneous, multicore SoCs and electronic systems.
Lots of information in 1 hour!