Benny Winefeld, Solutions Architect at Arteris IP, accepted the 1st Place Best Paper Award from the SNUG Technical Committee during SNUG Silicon Valley. There were 29 papers that competed for the best paper award.

In the photo above, Benny receives the award from the SNUG committee, from left to right: Ken Nelson, VP Field Support Operations; Benny Winefeld, Solutions Architect, Arteris IP; Tony Todesco, SNUG SV Technical Chair, AMD; and Deirdre Hanford, Co-GM, Synopsys.

Here are some excerpts for the paper:

“The concept of cell characterization for timing, power and area has been widely used in the IC industry since the advent of the logic synthesis. Years later, due to the growing adoption in SoC design, similar techniques were applied to hard IPs. The growing transistor counts of silicon chips combined with the ever increasing complexity make a powerful incentive for designers to work on higher abstract levels and use as many “off-the-shelf” components and subsystems as possible.

Some of these subsystems, such as Networks-on-Chip are only available as soft, configurable IPs. Predicting PPA behavior of “soft” IPs and their components can facilitate more efficient SoC  planning.

This paper proposed an approach where characterization of parametric NoC components is performed with machine learning methods based on actual accumulated synthesis results, obtained by running dc-topo with various input parameters – both logical and physical.

While it is still a work in progress, we believe this is a promising methodology augmenting the architectural design of modern Network-on-Chip with the early insight into its physical aspects.”

This paper will be made available soon online in the SNUG Proceedings at https://www.synopsys.com/community/snug/snug-proceedings.html.

Additional Arteris IP resources are available at https://www.arteris.com/resources.