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Arteris IP at DATE 2019

Arteris IP at DATE 2019 download

Location: Firenze Fiera, Florence, Italy
3.1 Executive Session 2: Panel
Date:
Tuesday, 26 March 2019
Time: 14:30 - 16:00
Location: Room 1

Arteris IP's CEO, K. Charles Janac joins this Executive Panel Session, "Semiconductor IP, Surfing the Next Big Wave"

Organisers:
Giovanni De Micheli, EPFL, CH, Contact Giovanni De Micheli
Jamil Kawa, Synopsys, US, Contact Jamil Kawa

Chair:
Raul Camposano, Sage Design Automation, US, Contact Raul Camposano

Semiconductor IP has made a great deal of progress since ARM was incorporated in 1990, almost thirty years ago, while the IC was breaking the 1-micron barrier, and power was becoming designers' biggest concern. Back then, semiconductor IP was "hard", physical-IP, which required complex porting to each and every different process technology. Over the last thirty years, and thanks to the transition from "hard" to "soft", synthesizable-IP, it has dramatically expanded, and now spans processors, interconnect, interface, FPGA, and complete sub-systems, and has become a critical enabler of modern systems-on-a-chip. Our industry is now moving to the 7/5 nanometer nodes: power remains a concern, but it is the lagging processors frequency, the latency across the processors, memory, and storage stacks, as well as the signal losses in electrical transmission lines that prevents breakthrough improvements. After decades of dominance by general purpose CPU and GPU, innovation is disrupting computing architectures: massively parallel Tensor Processing Units (TPU) are emerging that have demonstrated unprecedented performance; new memories are emerging that may complement 3D DRAM and NAND; new technologies are emerging such as super-conducting electronics and silicon photonics, which require an unprecedented level of collaboration to rapidly achieve the maturity levels required for the design and manufacturing of VLSI systems. This panel, moderated by EDA industry veteran Raul Camposano, will explore the challenges and the opportunities of semiconductor IP for the next decade.

Panelists:

  • Alessandro Cremonesi, STMicroelectronics, IT
  • K. Charles Janac, Arteris, US
  • Joachim Kunkel, Synopsys, US
  • Andrei Vladimirescu, Berkeley, US
  • Greg Yeric, ARM, US

Registration: https://www.date-conference.com/registration

For more information, please click here: http://www.arteris.com/flexnoc-ai-package

 
 

 

Topics: FPGA semiconductor Soft IP SoCs noc interconnect hard ip