Arteris Articles

Madelyn Miller

Madelyn Miller

Recent Posts by Madelyn Miller:

Semiconductor Engineering: Planning For Failures In Automotive

 Arteris IP's Kurt Shuler, VP of Marketing, comments on Bigger Chips in this latest Semiconductor Engineering:

Planning For Failures In Automotive

November 7th, 2019 - By Ann Steffora Mutschler

With more consolidation of functions within the ECUs in vehicles, the chips are getting bigger.

 In fact, they’re much larger and more sophisticated than
any chip in a cell phone, and have many more brains on it, noted Kurt Shuler, vice president of marketing at Arteris IP. “They’re more like something you would find in a data center, but it’s in your car. It’s got to sip power from a battery and it can’t have too much heat, so they’ve got all these different challenges. Then, if you look at the design teams that do this stuff, as design approaches change to anticipate failures, this is the reason why the traditional semiconductor companies are having trouble adapting — companies that have been incumbents and have done automotive chips for years.”

The ISO 26262 spec has been adapted to accommodate this in that fault injection can be done at a higher level than post synthesis, and can be run at the RTL functional level. “Still, getting some of the automotive guys to accept that this is acceptable is a challenge, but it’s progressing,” he added.

You can learn more by going to the Arteris IP Resources page and download presentations, technical papers, and view videos here; https://www.arteris.com/resources

Topics: SoC functional safety ISO 26262 semiconductor engineering AI kurt shuler noc interconnect SOTIF (ISO 21448 bigger chips

SemiWiki: Safety and Platform-Based Design

Kurt Shuler, VP Marketing at Arteris IP, updates Bernard Murphy of SemiWiki on some of the ways that safety and platform-based design interact, particularly where fail-operational functionality is required in autonomous or semi-autonomous systems, in this new SemiWiki blog:

Safety and Platform-Based Design

October 22nd, 2019 - By Bernard Murphy

Platform-based design, an approach to easily support multiple derivatives, opens some interesting new twists for safety-centric design. 

Bernard was at Arm TechCon as usual this year and one of the first panels he covered was close to the kickoff, hosted by Andrew Hopkins (Dir System Technology at Arm), Kurt Shuler (VP Marketing at Arteris IP) and Jens Benndorf (Managing Dir and COO at Dream Chip Technologies). The topic was implementing ISO 26262-compliant AI SoCs with Arm and Arteris IP, highly relevant since more and more of this class of SoC are appearing in cars. One thing that really stood out for me was the value of platform-based design in this area, something you might think would be old news for SoC design but which introduces some new considerations when safety becomes important.

You can learn more about this design by downloading the Arm TechCon presentation HERE.

Topics: SoC ARM semiconductor automotive automotive functional safety ArterisIP ISO 26262 compliance artificial intelligence AI semiwiki kurt shuler noc interconnect AI SoCs ASIL compliance

EE Times article, The Age of the Monster Chip

K. Charles Janac, President and CEO, at Arteris IP, authored this article on what is now defined as a "Monster Chip".

September 19, 2019 - by K. Charles Janac

What are the system designs that require a leap in SoC complexity? It’s not only big datacenter artificial intelligence (AI) chips, but also autonomous vehicles such as cars, trucks and drones; they are self-landing, reusable rockets; they are medical devices carrying out remote diagnostics; and they are connected machine tool controllers supporting smart manufacturing.

These chips are starting to be referred to as “Monster Chips” because of both the size and complexity.

Topics: semiconductor ADAS eetimes autonomous driving AI K. Charles Janac SoCs noc interconnect data center automation blockchain big chips

Semiconductor Engineering: In-System Networks Are Front And Center

 Arteris IP's Kurt Shuler, VP of Marketing, authored this article and offers his perspective on HotChips 2019 in this latest Semiconductor Engineering:

In-System Networks Are Front And Center

September 15th, 2019 - By Kurt Shuler

AI demands push innovation in design architectures and techniques.

 

This year’s HotChips conference at Stanford was all about artificial intelligence (AI) and machine learning (ML) and what particularly struck me, naturally because we’re in this business too, was how big a role on-chip networks played in some of the leading talks.

Giant leaps are being made in supporting new AI architectures, tuning them for optimum performance per milliwatt and embedding them effectively into traditional and novel SoC architectures.

You can learn more by reading my white paper titled, "Re-Architecting SoCs for the AI Era". Download is free; https://www.arteris.com/download-re-architecting-socs-for-the-ai-era

Topics: SoC functional safety ISO 26262 machine learning cache coherency semiconductor engineering AI kurt shuler noc interconnect SOTIF (ISO 21448 Hot Chips bigger chips