Much of the talk today in the system on chip (SoC) ASIC business is about how smaller critical dimensions are driving the use of more and more IP blocks on a single SoC. As the number of IP blocks increases, the act of assembling and physically manufacturing the SoC become Herculean. What’s the big deal?
Would you believe, Routing Congestion!?
It sounds kind of obvious, but the more IP blocks you have that need to be connected, the more wires you need to connect them. What isn’t as obvious is that routing congestion has 3 evil effects:
1. Poor performance
2. Longer, more uncertain schedules
3. Lower yields and higher costs
Evil #1: Poor Performance
Routing congestion is a major contributor to failed timing closure and failure to meet design frequency.
Failed Timing Closure
EDA routing tools use the less resistive upper metal layers for power supply and clock wires and are quickly consumed. Then these routing tools attempt to route long or timing-critical paths on more resistive middle and lower metal layers. The decreased cross-sectional area of the wires in the middle and lower metal layers leads to increased resistance which causes greater wire delays over longer distances.
Resistance in wires leads to:
- Wire delays
- Poor clock skew/slew
- Delays in global clock distribution
All of these, combined with the practice of using longer “dogleg” wire paths to avoid congested areas, cause timing closure issues.
Also, longer wires lead to more capacitance and therefore increased dynamic power dissipation. And using longer “dogleg” wire runs require pipeline or buffer stage logic that adds additional gates and increases leakage power.
Evil #2: Longer, More Uncertain Schedules
Wire routing congestion lengthens the time to close timing because the calculation of wire delays must include capacitive congestion effects, or the designer will not be able to identify the true critical paths in the SoC. Architects try to work around this problem by creating about 30% “white space” around each IP block to accommodate wire routing, but in congested areas this is often not enough.
Evil #3: Lower Yields, Higher Costs
Routing congestion increases the probabilities of manufacturing defects, lowering yields. Routing congestion often leads to the use of more vias to circumvent congested areas in the vertical direction. But vias are a major cause of yield loss is semiconductor manufacturing. Also, vias themselves create blockages which must be routed around, leading to Evils 1 and 2.
The Solution = Use Fewer Wires!
What if you could use fewer wires to connect the IP blocks in your SoC, all while using the same IP protocols you do today? You can.
You will learn how:
- To reduce the number of wires required for AMBA AXI by 50%
- To calculate routing congestion
- Current SoC trends increase the likelihood of routing congestion
This concise paper explains everything the reader needs to know to make an initial assessment of routing issues within his or her current SoC projects.
Photo Source: Apple A4 cross section showing metal lines (wires) and vias, FIB cut photo from www.chipworks.com