There has been a lot of confusion about the different standards for interchip connectivity, with many hardware developers of consumer electronics and mobile computing systems-on-chip wondering what to use. As an interconnect IP provider, I struggle with this every day when working with our customers. I wrote this article to share what I have learned.
[Note: Table below was update 10 April 2012.]
Why interchip connectivity?
The simplest answer is, “Because I want to connect two SoCs together on a PCB with as few traces and as little power consumption as possible.”
But there are other considerations:
- Are you connecting your own chips, or chips from other vendors? If from other vendors you will need to research the standards used in those chips. You’ll also need to make sure you match voltages and timings.
- How many pins do you have available? Some standards like USB HSIC and MIPI LLI only need 2 pins, while others like C2C require at least 24. Application processors are usually more pin-constrained than companion chips or mobile phone modems.
- How much power can you burn? Only C2C does not require a PHY. USB HSIC still requires a PHY even though it doesn’t require a full transceiver setup like a regular USB connection. MIPI HSI and LLI also require a PHY. Applications processors can usually accommodate another PHY, but companion chips like mobile phone modems or LTE coprocessors may be area or power limited.
- Do you want to share memory between the two chips? C2C and MIPI LLI are very low latency interfaces that are fast enough for a mobile phone modem or companion chip to share an application processor’s RAM and to maintain enough read throughput and low latency for cache refills. This enables remote configuration and memory mapped transfers as if the two chips were a single chip.
- What is the impact on your software ? C2C and LLI are memory-mapped interfaces that only require software intervention to set them up: The actual data transfers do not require any software driver intervention, and one of the chips does not require a driver at all.
What are the interchip connectivity standards?
USB 2.0 High Speed Inter Chip (HSIC)
HSIC was adopted as a standard by the USB Implementers Forum in 2007. It is a chip-to-chip variant of USB 2.0 that eliminates conventional USB PHYs. The HSIC PHY uses about 50% less power and 75% less area compared to traditional USB 2.0 PHYs. HSIC uses 2 signals at 1.2v and has a throughput of 480Mbit/sec using 240MHz DDR signaling. Maximum PCB trace length for HSIC is 10cm. It does not have low enough latency to support RAM memory sharing between two chips.
MIPI High-speed Synchronous Serial Interface (HSI) v1.0
HSI was created in 2003 and is now managed by the MIPI Alliance. It is the granddaddy of mobile phone inter-chip interconnects and is still present leading SoCs like TI’s OMAP 5 platform. HSI operates at 1.2 or 1.8 volts and has throughout of 200 Mbit/sec. It does not have low enough latency to support RAM memory sharing between two chips.
MIPI UniPro/UniPort v1.4
The UniPro specification was first released in 2007. UniPort is simply UniPro combined with a MIPI D-PHY or M-PHY. A 2-wired differential D-PHY or M-PHY interface supports a maximum data transfer rate of 800 Mbit/sec, but the UniPro data lane is scalable from 1 to 4 lanes for a total throughput of 3.2 Gbit/sec. UniPro is not low latency enough for RAM sharing.
MIPI Low Latency Interface (LLI)
The MIPI LLI specification will be released in 2011. Its primary purpose is to allow sufficient performance to enable sharing a DRAM memory between 2 chips for data and programs. The main motivation is electronic bill of materials (eBoM) cost reduction. MIPI LLI requires only 2 or 4 pins but does require a MIPI M-PHY capable of Gear 2 for mobile phone use models. Round trip latency is targeted to be 80 nanoseconds using 8 pins in Gear 3, allowing a mobile phone modem or companion chip to share an application processor’s RAM. This saves a minimum of $2 in device eBoM cost, saves PCB space, and reduces device complexity. Unidirectional throughput is 2.9 Gb/sec per lane using MIPI M-PHY Gear 2.
C2C has been available since 2010 and is a product containing technology from Texas Instruments and Arteris. It was created to allow DRAM memory sharing for reduced eBoM cost through a very low latency interface. C2C does not require a PHY, however, unlike MIPI LLI’s 2 or 4 pin requirement, C2C requires about 30 pins total in a mobile phone use model (16 transmit pins, 8 receive pins, plus clock and power pins). The interface can use existing DDR pads and is LPDDR I/O compliant. Round trip latency is 100ns, allowing a modem or companion chip to share an application processor’s memory. At 100,000 gates, C2C is very small. It requires 1.2 or 1.8 volts and has throughput of 6.4 Gb/sec at 200 MHz DDR speeds and using 16 pins.
Which interchip connectivity option to choose?
The decision on what inter-chip connectivity standard to use is dependent upon a product’s specific use cases and requirements, as well as the interfaces available in the companion products with which it will connect. You will need to understand ahead of time whether you require basic connectivity, or whether you require more exotic features like the memory sharing capabilities delivered by C2C and LLI, and how much embedded software impact this will have on your system.
Keep in mind that the companion chips with which you would like to connect may have different connectivity requirements and roadmaps than your own products. Therefore it is important to coordinate with the organizations that create these companion chips, whether these teams are in your company or external.As featured in: