Today in the IP and EDA business, I hear “knock” all the time, except people mean “NoC.” It seems everybody wants a NoC, or wants to offer you a NoC. I’m here to tell you that NoC is not a noun.
A network-on-chip is a technology approach that can be used to transfer data and commands in many domains. When people in the IP and EDA businesses say NoC, they are usually referring to the means to control a SoC interconnect fabric, either within a chip, between chips, or both. In short, it is an adjective that describes a type of SoC interconnect solution.
As SoC makers add more IP blocks to a chip, such that points A and B are joined by points Z, AA, and AB, traditional bus and crossbar means to communication become very inefficient, resulting in serious pain to architects, designers, and integrators: Massive numbers of wires, failed timing closure, increased heat and power consumption, and spaghetti-like routing congestion leading to increased die area. These problems are compounded when there are IP changes late in the design cycle or when management expects the next derivative version of the chip to be on time and risk free because, “we only changed a few IP blocks.”
Now let’s add the fact that there are four major IP interface standards and many SoC makers have their own, too. Plus, we want the highest priority for real-time IPs, the required throughput for media and communications IP, and lowest latency for CPU cache refills from off-chip memory. And we need to make sure our chip can meet its external communication requirements with the fewest number of pins, pads and wires possible. It’s no surprise that for every dollar an SoC maker spends on IP, two to three dollars are spent connecting and integrating it!
A well thought out NoC approach to SoC IP interconnection is an ideal solution to these challenges. Translating to a simple, packet-based interconnect protocol at the edge of each IP block gives the ability to plug-and-play IPs with different interconnect protocols. It also avoids hierarchical mixed-protocol interconnects and the need to frequently translate and traverse different bus interfaces. These may introduce additional latency and make power management more challenging. Packet-based protocol also results in fewer and shorter wires, reducing routing congestion, easing timing closure and shrinking the gate count and area of the interconnect and SoC.
Packetizing and bursting data reduces the number of wires down to one half. Locating the interconnect logic closest to each IP block results in fewer gates, fewer and shorter wires, and a more compact chip floor plan. Having the option to configure each connection’s width, and each transaction’s dynamic priority assures meeting latency and bandwidth requirements.
What this means is that a NoC is not a NoC. Different companies have different approaches to their interconnect solutions, and some use facets of network-on-chip technologies. It is important for each SoC development team to look closely at what pain they are feeling and what goals they want to meet with each design, then choose the interconnect solution that works best to meet their goals.
So we can all call our interconnect IPs a fabric or interconnect or even a bus. Just be prepared to be specific if you choose to call it a NoC.