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Free semiconductor IP isn't free: White paper on SoC economics

WhFree SoC economics white paper about NoC interconnect benefitsenever we purchase a durable item like a house or a car, we tend to look not only at the initial sales price, but also what are the costs and benefits over time. However, we don’t always take the same methodical “net present value” approach when dealing with companies that supply semiconductor intellectual property (IP) to our development teams.

A recent white paper by Objective Analysis, a semiconductor market research firm, pointed out the fallacy of this kind of economic behavior. They assessed data from four major semiconductor companies’ use of network on chip (NoC) interconnect IP for SoC designs.  

The danoc interconnect soc economics CTAta were clear: The economic benefits of using network on chip interconnect IP were more than 10x the license price for the IP, and also provided a much higher ROI than internally developed or “free/bundled” interconnect IP.

 

Why do the benefits of NoC interconnect IP dwarf the initial license costs?

The paper goes into much more detail, but there are four areas where the customers gained huge economic benefits from using network on chip interconnect IP:

  1. Die size –50% reduction in the number of metal lines/wires; 30% reduction in gate count; typically resulted in a 2 to 5% reduction in die size. This is about a 10 cents per die cost savings for a high volume mobile phone applications processor!
  2. Power consumption – Fewer interconnect wires and gates to drive; easier to implement power management schemes like dynamic voltage and frequency scaling (DVFS).
  3. Project design time – Easier to configure than a hybrid bus or crossbar interconnect; integrated SystemC modeling allowing fast iterations to ensure interconnect meets requirements; fewer wires reduces backend wire routing congestion and timing closure issues.
  4. Performance – Faster frequencies than hybrid busses or crossbars; Advanced QoS for bandwidth, latency and security requirements.

One issue the paper doesn’t examine is the risk a semiconductor maker bears if a chip is late. The upfront license fees are small compared to the benefits and cost savings, and are really small compared to the lost revenue if a chip is late. I’ll be writing about how to measure this lost revenue in a future article.

Download the free SoC economics whitepaper here.

Topics: SoC economics interconnect IP costs benefits free IP white paper download