When discussing system-on-chip (SoC) design with my semiconductor design and software development peers, the conversation eventually gets around to the problem of, “There’s just too much IP!” The feelings I hear border on exasperation at the problem of integrating IP on today’s large SoCs. Engineers who were once paid to write lines of Verilog or C code from scratch are now spending much of their time tying together commercial hardware IP and the associated software. Their jobs have changed, and they’ve had to acquire new skills and new tools to be successful.
Stepping back for a second, one could assume that all the semiconductor industry consolidation has resulted in fewer commercial IP choices (See “The Semiconductor Industry Needs an IP Switzerland”, http://info.arteris.com/blog/bid/96393/The-Semiconductor-Industry-Needs-an-IP-Switzerland). And that would be wrong. Even though there are fewer small companies offering design IP, the percentage of commercial IP in a SoC has continued to climb, and is usually more than half the chip (depending on how you measure it: logic gates, monetary value, etc.).
The use of commercial IP in SoCs can only increase. With each shrink in process node, design teams consolidate what used to be 2 or 3 standalone chips into one chip. This now results in SoCs that have 2 to 3 billion gates. In addition to this “chip real estate is cheaper” trend, some companies that solely offered semiconductors are now licensing chip functionality to other SoC makers as design IP.
Given that the use of commercial design IP will continue to grow, the problem becomes how to integrate it. Part of the problem can be addressed with the help of existing means such as increased automation, standardized IP information schema (like IP-XACT), and greater use of system-level modeling. All these means are discussed in the article, “Integration Demands Automation” by Ann Steffora Mutschler (http://chipdesignmag.com/sld/blog/2013/01/31/integration-demands-automation/).
However, the most important means to address the problem of integrating hundreds of IP blocks is to smartly use another IP: The interconnect fabric.
The interconnect fabric is the one IP that touches every subsystem and every functional block on a chip. When the design team configures the various IP blocks on a chip and ties them into the interconnect, this information (configuration options, transaction protocols, memory locations, etc.) can be stored by the interconnect IP and associated tools and used to automate the creation of system models, verification environments and even software drivers. In effect, the interconnect fabric acts as the “golden model” that describes the assembly parameters of the SoC.
Therefore, the way to solve the “more IP” problem is to carefully select what is the most important IP with regards to SoC assembly, modeling and verification: The interconnect fabric.