FPGAs Becoming More SoC-Like

Lines blur as processors are added into traditional FPGAs, and programmability is added into ASICs.

Ty Garibay, CTO of Arteris IP is well acquainted with this evolution. “Historically, Xilinx started down what became the Zynq path in 2010, and they defined a product that was going to essentially incorporate the hard macro of an Arm SoC into a corner of an existing FPGA,” he said. “Altera then hired me to do essentially the same thing. The value proposition was that an SoC subsystem was something many customers would want, but because of the nature of SoCs and especially processors, they don’t fit synthesis well onto an FPGA. Embedding that level of functionality into the actual programmable logic was prohibitive, as it used almost the whole FPGA just for that function. But it could be put in as a small or trivial part of the overall FPGA chip as a hard function. You gave up the ability to have truly reconfigurable logic for that SoC, but it was programmable as a software, so it changes function in that way.”

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That meant it was possible to have a software programmable function, a hard macro and then a hardware-programmable function in the fabric and they could work together, he said. “There were some pretty good markets for that, especially in low-cost automotive control—places where there was traditionally a medium-performance microcontroller-type device next to the FPGA, anyway. The customer would just say, ‘I’m just gonna roll that whole function into the hard macro on the FPGA die to reduce board space, reduce BOM, lower the power.’”

“FPGA vendors have been continuing to grow the die, but also continuing to add more and more hard logic that is deemed to be generally usable by a significant percentage of the customer base,” Garibay said. “What’s happening today is an extension of that into the software programmable side of it. Most of the things that were added before this Arm SoC were different forms of hardware, mostly to do with I/O, but also DSPs that it made sense to try to just save programmable logic gates by hardening them because there is enough planned utility.”

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