Semiconductor Engineering: Interconnect Challenges Grow, Tools Lag

by Madelyn Miller, On Jun 15, 2020

Interconnect Challenges Grow, Tools Lag 

June 15th, 2020 – By Brian Bailey

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More data, smaller devices are hitting the limits of current technology. The fix may be expensive. 

Chips are growing. “Ten years ago, the interconnect would be concerned with about 10K gates,” says Benoit de Lescure, CTO for Arteris IP. “Now they need to interconnect 10M gates on a chip, so there’s been a very significant increase in complexity. The number of clients on the interconnect has increased.”

To read the entire SemiEngineering article, please click here: https://semiengineering.com/interconnect-challenges-grow-tools-lag/

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