Arteris Articles

Semiconductor Engineering: More Nodes, New Problems

Benny Winefeld, solutions architect at Arteris IP, adds additional commentary to this Semiconductor Engineering article:

More Nodes, New Problems

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April 26th, 2018 - By Ann Steffora Mutschler

Acceleration of advanced processes, skyrocketing complexity and cost, and concerns about IP availability are raising some difficult questions.

  Download peer-reviewed Springer journal paper about Arteris FlexNoC QoS

From Benny: “Hard IP migration went from difficult to nearly impossible. Soft IP migration went from trivial to difficult, because RTL which used to be fine for node N-1 may easily become non-implementable under physical constraints of node N. Arteris NoC IP is always soft as it fills the space between other IPs on the chip, so hard IP migration doesn’t apply to us.

How do we address newfound difficulties of soft IP migration? We don’t just give customers the RTL but provide a physically-aware software generating RTL and collateral (synthesis scripts, etc.) tuned for constraints of a given tech node. Soft IP still needs to go through the backend flow, but we make this process easier”

To read the entire article, please click here:
https://semiengineering.com/more-nodes-new-problems

Topics: SoC design neural networks NoC technology semiconductor engineering arteris ip latency bandwidth Soft IP