Arteris Articles

Semiconductor Engineering: AI Chips: NoC Interconnect IP Solves Three Design Challenges

 Arteris IP's Kurt Shuler warns that regular topologies, large chips, and huge bandwidths are considerations in AI-centric chips in the date center.

AI Chips: NoC Interconnect IP Solves Three Design Challenges  

January 10th,  2019 - By Kurt Shuler

se_logo-8New network-on-chip (NoC) interconnect IP is now available for artificial intelligence (AI) systems-on-chip (SoC). Arteris IP launched the fourth generation of FlexNoC interconnect IP with a new AI package.

The new NoC technology benefits emerging AI chip architectures in three main ways: automatically generating regular topologies, effectively managing the data flows of large chips with long wires and enabling large on- and off-chip bandwidths.

To learn more, please visit the FlexNoC AI Package page; https://www.arteris.com/flexnoc-ai-package and the Resources page: https://www.arteris.com/resources

To see the entire on the SemiEngineering page, please click here:

https://semiengineering.com/ai-chips-noc-interconnect-ip-solves-three-design-challenges

 

Topics: AI chips semiconductor AI automotive neural networks ML AI SoC Designers flexnoc ai package VC-Links synchronous virtual channels noc interconnect