Arteris Articles

Semiconductor Engineering: When Bugs Escape

Chirag Gandi, Director of Verification at Arteris IP, chats with Brian Bailey in this Semiconductor Engineering article:

When Bugs Escape

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July 26th, 2018 - By Brian Bailey

The ability to find bugs has not kept up with the growing complexity of systems. Bugs are more likely to end up in products than ever before.

Verification methodologies have evolved over time. “Today, the industry does layered verification,” states Chirag Gandhi, director of verification for Arteris IP. “It starts at the unit level and there are assumptions on the inputs and outputs at the unit level. It then goes to the sub-system and full-system level. As many layers are defined in the hierarchy as needed. It can go to emulation where it can exercise the use-case that the chip is intended for. The next level above that is silicon, where you have the actual silicon and you do testing before you ship the product. You try to cover as many cases as possible to make sure that you don’t have corner-case bugs.”

Most of the existing verification tools focus on functional errors. “Ten years ago verification engineers only cared about functional errors, and there was little focus on performance,” says Gandhi. “Today, it is part of the verification planning phase. You have to look at the interactions between units to see if it causes problems that result in performance bugs.”

  Download peer-reviewed Springer journal paper about Arteris FlexNoC QoS

To read the entire article, please click here:
https://semiengineering.com/when-bugs-escape

Topics: SoC semiconductor semiconductor engineering arteris ip interconnects deadlocks emulation silicon RTL formal verification layered verification corner-case bugs