Arteris Articles

Semiconductor Engineering: Getting Serious About Chiplets

Ty Garibay, CTO of Arteris IP stated, “Not only is it hard to justify the cost of these advanced nodes, it’s also hard to find people that can do it", in this Semiconductor Engineering article:

Getting Serious About Chiplets

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January 8th,  2018 - By Ann Steffora Mutchler

The idea of using chiplets, with or without a package, has been circulating for at least a half-dozen years, and they can trace their origin back to IBM’s packaging scheme in the 1960s. It is now picking up steam, both commercially and for military purposes, as the need for low-cost semi-customized solutions spreads across a number of new market opportunities. 

“If you look at where things are going, soon it will be down to four or five companies that can even do large scale 7nm or 5nm design with any expectation of getting it to work and making money,” said Ty Garibay, CTO of Arteris IP. “Not only is it hard to justify the cost of these advanced nodes, it’s also hard to find people that can do it. It’s a difficult task, and you have a limited number of talented designers that are going to be able do it for you. These big companies may consider building the active substrate at 7nm or 5nm if yields are good enough, and then using chiplets to implement high speed IO or other special functions. However, if a startup can create a 100X improvement and still have the performance advantage because their smart, whether the function is implemented in 22nm and gives up 30% or 40% performance probably doesn’t matter. They are still ahead. Maybe then they can get enough money to get into the game at the more advanced nodes with that first product. But you can get into the game with a far smaller investment up front.”

  Download peer-reviewed Springer paper

To read the entire article, please click here:
https://semiengineering.com/getting-serious-about-chiplets/

Topics: System-on-Chip Ty Garibay semiconductor engineering chiplet