Arteris Articles

Semiconductor Engineering: The Race To Multi-Domain SoCs

 Arteris IP's CEO looks at how automotive and AI are Altering chip design in this article in Semiconductor Engineering;

The Race To Multi-Domain SoCs

February 7th,  2019 - By Ed Sperling

K. Charles Janac, president and CEO of Arteris IP, sat
down with Semiconductor Engineering to discuss the impact of automotive and AI on chip design. What follows are excerpts of that conversation.

SE: What do you see as the biggest changes over the next 12 to 24 months?
Janac: There are segments of the semiconductor market that are shrinking, such as DTV and simple IoT. Others are going through an investment phase, including automotive, AI/machine learning and China. You really want to be focused on those segments. 

SE: So does IP that’s being developed today look radically different than it did five years ago?
Janac:
Yes, everything is getting amazingly complex. What people are building right now are multi-domain SoCs. The CPU, which used to do all the work, does relatively less work. There are accelerators for vision and data analysis outside of the CPU subsystem. There are machine learning sections, some general-purpose, some very specific, all on-chip. There is a memory subsystem with very high-bandwidth memory and low latency. There also is functional safety. You need tremendous performance because a car is a supercomputer on wheels. The car has to be very efficient, because you need to deliver that compute power without water cooling. Power management becomes very sophisticated. And then there are functional safety and security subsystems to keep these safe from environmental and man-made issues.

SE: Where does the network on chip (NoC) fit into all of this?
Janac: All data goes through the NoC of the chip. There are opportunities for generating value from that. But the increase in complexity is increasing the number and sophistication of the interconnect parts of the chip. Before, you may have had networks on chip. Now you may have 20 or 30.

Topics: semiconductor AI automotive neural networks ML AI SoC Designers flexnoc ai package noc interconnect chiplets ADAS LIDAR

Semiconductor Engineering: ISO 26262:2018, 2nd Edition: What Changes?

 Arteris IP's Kurt Shuler, vice president of marketing, delivers a recent update for the ISO 26262 standard in this blog in Semiconductor Engineering;

ISO 26262:2018, 2nd Edition: What changes?

February 7th,  2019 - By Kurt Shuler

The safety standard is now clearer for IP-based designs and those happening across multiple companies.

If you’re involved somehow in design for automotive electronics, you probably have more than a cursory understanding of the ISO 26262 standard. What your organization is working from is most likely the 2011 definition. The most recent update is formally known as ISO 26262:2018, less formally as ISO 26262 2nd Edition.

Standards should evolve, but what changed and why? I’ve been a member of the ISO 26262 working group for many years, and particularly involved in how it should be interpreted for IP, and I’ve got to tell you, I have struggled. 

From my perspective, it was originally written around an implicit expectation that chips are built from scratch entirely within one organization, and this is a dated assumption. There was also not enough guidance for IP-based design or design distributed across multiple companies or sites. The workaround for an IP supplier has been to use the Safety Element out of Context (SEooC) mechanism. But this depends heavily on human interpretation, by the component vendor on what may be relevant to the integrator and vice-versa, with little guidance from the 2011 version of the standard. I complained (whined?) quite a bit to the committee about these problems and they eventually invited me to the working group. I wasn’t the only one confused and other people joined, and we seem to have had an impact; our efforts have resulted in a lot more clarification, organization and practical examples in the latest standard. I think the new Part 11 of the updated standard provides a lot more detail and useful examples for us in the semiconductor and semiconductor IP industry.

For more information about ISO 26262:2018 Part 11, download the 39-slide Arm TechCon presentation titled, “Fundamentals of ISO 26262 Part 11 for Semiconductors,” by Arteris IP Functional Safety Manager Alexis Boutillier and ResilTech Scientific Advisor Dr. Andrea Bondavalli, or watch my very popular SemiEngineering “Tech Talk: ISO 26262 Drilldown” video.

Topics: AI chips semiconductor AI automotive neural networks ML AI SoC Designers flexnoc ai package noc interconnect ISO 26262 certification

Semiconductor Engineering: Chasing Reliability In Automotive Electronics

 Arteris IP's Kurt Shuler, vice president of marketing has authored a paper about ISO 26262 and comments in this article;

Chasing Reliability In Automotive Electronics 

January 15th,  2019 - By Susan Rambo and Ed Sperling

Supply chain changes, resistance to sharing data and technology unknowns add up to continued uncertainty.

"Traditional semiconductor vendors who are making or designing chips to enable autonomous driving applications are nowadays sometimes competing with Tier-1 electronics system designers and OEMs, who may be making their own chips or providing explicit requirements to their semiconductor vendor partners. Additionally, new entrants like Uber, Way and Apple are designing their own complete systems, despite their relative lack of experience in the automotive industry. ISO 26262 mandates high levels of collaboration and information sharing throughout the value chain that may be unfamiliar to new entrants."

The ISO 26262 standard is snapshot of issues and the lengths the whole supply chain has to go. Collaboration is key. Communication is part of the safety standards up and down the automotive safety critical supply chain now. It’s built into the standards.

Sharing knowledge of a supplier’s crown jewels—intellectual property—has to happen among suppliers and auto OEMs. “Participants in the semiconductor and software supply chains are usually secretive about how their IP was developed and how it works in detail,” said Shuler. Suppliers should remember that the “your customer still has an obligation to confirm your compliance with ISO 26262.”

To learn more, please download this technical paper, Fundamentals of Semiconductor ISO 26262 Certification: People, Process and Product.

Topics: AI chips semiconductor AI automotive neural networks ML AI SoC Designers flexnoc ai package noc interconnect ISO 26262 certification

Semiconductor Engineering: AI Chips: NoC Interconnect IP Solves Three Design Challenges

 Arteris IP's Kurt Shuler warns that regular topologies, large chips, and huge bandwidths are considerations in AI-centric chips in the date center.

AI Chips: NoC Interconnect IP Solves Three Design Challenges  

January 10th,  2019 - By Kurt Shuler

New network-on-chip (NoC) interconnect IP is now available for artificial intelligence (AI) systems-on-chip (SoC). Arteris IP launched the fourth generation of FlexNoC interconnect IP with a new AI package.

The new NoC technology benefits emerging AI chip architectures in three main ways: automatically generating regular topologies, effectively managing the data flows of large chips with long wires and enabling large on- and off-chip bandwidths.

To learn more, please visit the FlexNoC AI Package page; https://www.arteris.com/flexnoc-ai-package and the Resources page: https://www.arteris.com/resources

Topics: AI chips semiconductor AI automotive neural networks ML AI SoC Designers flexnoc ai package VC-Links synchronous virtual channels noc interconnect