Arteris Articles

Semiconductor Engineering: Variables Complicate Safety-Critical Device Verification

Kurt Shuler, Vice President of Marketing at Arteris IP participates in this new "Experts at the Table" article in Semiconductor Engineering:

Variables Complicate Safety-Critical Device Verification 

July 1st, 2020 - By Ann Steffora Mutschler

What's the best way to approach designs like AI chips for automotive that can stand the test of time? 

 
SE: Where does the industry stand with the task of verifying safety-critical devices today?
 
Kurt Shuler responds, "At the chip level we still have a situation where the verification people and methodologies are separate from the functional safety people and methodologies. This results in some overlap and rework. As tools and data interchange standards (like IEEE P2851 being led by both IEEE and Accellera) mature, we’ll be able to have more automation where functional safety validation through fault injection can be executed as part of regular verification processes. This will help everyone in the industry have more confidence that products don’t regress in diagnostic coverage as new versions are developed and will provide integrators/users of safety-critical systems to more easily perform fault injection validation of safety mechanisms if they desire."
 
Topics: SoC ISO 26262 automotive NoC technology semiconductor engineering ASIL D AI chips noc interconnect IP market IEEE P2851 fault injection

Semiconductor Engineering: A Promising Future For Interconnect IP

Rich Wawrzyniak of Semico Research describes the market drivers for advanced multicore SoC architectures and the critical role of NoC interconnect semiconductor intellectual property (IP) in this Semiconductor Engineering article:

A Promising Future For Interconnect IP

March 18th, 2020 - By Rich Wawrzyniak

Complexity of SoC designs continues to 

increase primarily due to increased demand for functionality and performance in all electronic devices. Studies that Semico Research has conducted on the SoC design landscape shows the number of discrete SIP blocks has continued to rise in response to increased market requirements from new applications and richer feature sets.

Topics: SoC NoC technology semiconductor engineering AI chips noc interconnect IP market

Semiconductor Engineering: ISO 26262:2018, 2nd Edition: What Changes?

 Arteris IP's Kurt Shuler, vice president of marketing, delivers a recent update for the ISO 26262 standard in this blog in Semiconductor Engineering;

ISO 26262:2018, 2nd Edition: What changes?

February 7th,  2019 - By Kurt Shuler

The safety standard is now clearer for IP-based designs and those happening across multiple companies.

If you’re involved somehow in design for automotive electronics, you probably have more than a cursory understanding of the ISO 26262 standard. What your organization is working from is most likely the 2011 definition. The most recent update is formally known as ISO 26262:2018, less formally as ISO 26262 2nd Edition.

Standards should evolve, but what changed and why? I’ve been a member of the ISO 26262 working group for many years, and particularly involved in how it should be interpreted for IP, and I’ve got to tell you, I have struggled. 

From my perspective, it was originally written around an implicit expectation that chips are built from scratch entirely within one organization, and this is a dated assumption. There was also not enough guidance for IP-based design or design distributed across multiple companies or sites. The workaround for an IP supplier has been to use the Safety Element out of Context (SEooC) mechanism. But this depends heavily on human interpretation, by the component vendor on what may be relevant to the integrator and vice-versa, with little guidance from the 2011 version of the standard. I complained (whined?) quite a bit to the committee about these problems and they eventually invited me to the working group. I wasn’t the only one confused and other people joined, and we seem to have had an impact; our efforts have resulted in a lot more clarification, organization and practical examples in the latest standard. I think the new Part 11 of the updated standard provides a lot more detail and useful examples for us in the semiconductor and semiconductor IP industry.

For more information about ISO 26262:2018 Part 11, download the 39-slide Arm TechCon presentation titled, “Fundamentals of ISO 26262 Part 11 for Semiconductors,” by Arteris IP Functional Safety Manager Alexis Boutillier and ResilTech Scientific Advisor Dr. Andrea Bondavalli, or watch my very popular SemiEngineering “Tech Talk: ISO 26262 Drilldown” video.

Topics: semiconductor automotive neural networks ISO 26262 certification AI AI chips flexnoc ai package noc interconnect ML AI SoC Designers

SemiWiki: Why High-End ML Hardware Goes Custom

Kurt Shuler, VP Marketing at Arteris IP,  provides more insight into what's happening in this highly dynamic space in the latest SemiWiki blog written by Bernard Murphy (SemiWiki):

Why High-End ML Hardware Goes Custom

January 30th, 2019 - By Bernard Murphy

In a hand-waving way it’s easy to answer why any hardware goes custom (ASIC): faster, lower power, more opportunity for differentiation, sometimes cost though price isn’t always a primary factor. But I wanted to do a bit better than hand-waving, especially because these ML hardware architectures can become pretty exotic, so I talked to Kurt Shuler, VP Marketing at Arteris IP, and I found a useful MIT tutorial paper on arXiv. Between these two sources, I think I have a better idea now.

Start with the ground reality. Arteris IP has a bunch of named customers doing ML-centric design, including for example Mobileye, Baidu, HiSilicon and NXP. Since they supply network on chip (NoC) solutions to those customers, they have to get some insight into the AI architectures that are being built today, particularly where those architectures are pushing the envelope. What they see and how they respond in their products is revealing.

You can learn more about what Arteris IP is doing to support AI in these leading-edge ML design teams HERE. They certainly seem to be in a pretty unique position in this area.

 For more information, download this FlexNoC AI Package datasheet; http://www.arteris.com/flexnoc-ai-package

Topics: NoC semiconductor semiwiki kurt shuler AI chips flexnoc ai package accelerators noc interconnect ML-centric design