Arteris Articles

New! Arteris IP Technical Paper, Re-Architecting SoCs for the AI Era

Kurt Shuler, VP of Marketing at Arteris IP has written this 10-page technical paper titled, "Re-Architecting SoCs for the AI Era".

August 29, 2019 - by Kurt Shuler

Abstract:
The growth of artificial intelligence (AI) demands that semiconductor companies re-architect their system on chip (SoC) designs to provide more scalable levels of performance, flexibility, efficiency, and integration. From the edge to data centers, AI applications require a rethink of memory structures, the numbers and types of heterogeneous processors and hardware accelerators, and careful consideration of how the dataflow is enabled and managed between the various high-performance IP blocks.

Topics: functional safety ISO 26262 semiconductor machine learning autonomous driving artificial intelligence AI SoCs kurt shuler noc interconnect ML dataflow

EE Times article, The Gatekeeper of a Successful Design is the Interconnect

K. Charles Janac, President and CEO, at Arteris IP, authored this article on how an effective interconnect makes delivering a complex SoC easier, more predictable, and less costly.

August 25, 2019 - by K. Charles Janac

An interconnect handles various types of traffic inside an SoC and is a mechanism for effective IP block integration. The interconnect is the most configurable IP in the SoC — typically changing many times during a project and nearly always changing between projects. It also plays a vital role in security and functional safety because it carries most of the SoC data and contains nearly all the SoC’s long wires and system-level services, including quality of service (QoS), visibility, physical awareness, and power management. The interconnect enables cache coherency in multiprocessor SoCs, high-performance and bandwidth levels in advanced driver assistance systems (ADAS) automotive chips and networking SoCs, and ultra-low power in long-running consumer devices.

Topics: semiconductor eetimes advanced driver assistance systems adas autonomous driving AI K. Charles Janac SoCs noc interconnect ML data center automation

EE Times article, SoC Interconnect: Don't DIY!

Kurt Shuler, VP Marketing at Arteris IP, explains why a DIY approach to building your own configurable interconnect IP product is not as easy as one may think.

June 13, 2019 - by Kurt Shuler

The recent market consolidation might have some companies considering whether this is a do-it-yourself (DIY) project that your company should consider taking on. Whether it’s a simple crossbar switch or a full-function network-on-chip (NoC) architecture for advanced SoCs, all that’s needed are the right people with the right knowledge and a big budget; eventually, it could happen. But the question isn’t can you do it? It’s should you do it?

Topics: semiconductor eetimes autonomous vehicles AI automotive design SoCs kurt shuler noc interconnect ML/AI

Semiconductor Engineering: Big Shift In Multi-Core Design

 Arteris IP's Kurt Shuler, Vice President of Marketing, adds commentary in this article in Semiconductor Engineering.

Big Shift In Multi-Core Design

April 3rd, 2019 - By Ann Steffora Mutschler

System-wide concerns in AI and automotive are forcing hardware and software teams to work together, but gaps still remain.

Minding the gap
There are indications that mindset is beginning to change, particularly in markets such as automotive where systemic complexity extends well beyond a single chip or even a single vehicle.

“In the past, if you were a software engineer, the thinking was, ‘I have this chip available. Here’s what I can produce with my software,'” said Kurt Shuler, vice president of marketing at Arteris IP. “Nowadays, especially in the ADAS side of things that have an AI component or some kind of programmable object detection for the ADAS functionality, or an AI chip—whether it’s for the data center, edge, inference or training—the thinking has shifted more to system-design decisions. If this is designed with this given set of software algorithms, it is clear what needs to happen at a system level from the hardware and software point of view. At what level of detail should I optimize this hardware for the particular software I expect to run? This means the hardware and the software are now much more tightly integrated in those use cases than they probably have ever been unless it’s a very detailed embedded application. So now, in the early stages of design for these types of chips, whether it’s the autonomous driving chips or the AI chips, the software architect is in there, too.”

This is a definite sign of progress. “Before, they didn’t care,” Shuler said. “The layer/API between hardware and software is becoming less generic and more specific for those kinds of use cases, solving those kinds of problems. What that means, though, is there are software guys who went to Stanford and trained on Java script and have no idea what a register is. Then there are hardware guys who have no idea what a hypervisor or object-oriented programming is.”

For more information on AI, please click on the Arteris FlexNoC AI Package webpage: http://www.arteris.com/flexnoc-ai-package.

Topics: SoC software automotive ADAS autonomous driving semiconductor engineering AI hardware noc interconnect