Arteris Articles

Arteris IP is Hiring a Design Verification Engineer, Campbell, CA

Featured Position!

Design Verification Engineer in
Campbell, CA


Do you want to contribute to the backbone of the some of the world's most popular SoCs?

You will work with an expert team to design and deliver interconnect & memory hierarchy solutions for some of the world's most sophisticated mobile, telecom, automotive, and consumer SoC designs. You'll create designs in a powerful language that blends traditional RTL with leading-edge software to provide extremely configurable, testable, and high-quality solutions. You’ll go home at the end of the day amazed at all the places where your creations end up. You will have the opportunity to be part of a proven-successful startup, and to influence development environment, architecture, verification, and everything in-between – you’ll no longer be stuck in a silo or just a cog in the machine. Your co-workers will be an experienced team of industry experts that love what they do.

Topics: software jobs arteris ip noc interconnect job SoC designs C++ Java logic simulators

Semiconductor Engineering: CEO Outlook: 2020 Vision

 Arteris IP's CEO, Charlie Janac, is quoted in a 2020 survey of CEOs from across the country in this Semiconductor Engineering article:

CEO Outlook: 2020 Vision

January 6th, 2020 - By Ed Sperling

5G, China and AI are prominent, but big changes are coming everywhere.

 

“In 2020, highway driving starts to become real for autonomous vehicles,” said K. Charles Janac, CEO of ArterisIP. “You’re also going to see more applications for machine learning and AI emerge. Right now, there is too much money being spent on this by big Internet companies that are doing a lot internally. Those investments will shift. You’ll also see 5G becoming very important. We will need that for the last mile. The other killer app is cyber security, and this is one that is somewhat worrisome because we’re starting to see 5G and machine learning being used to track entire populations.”

To learn more, please download this Technical Paper on "Re-Architecting SoCs for the AI Era", please go here; https://www.arteris.com/download-re-architecting-socs-for-the-ai-era

Topics: SoC Networks-On-Chip autonomous vehicles semiconductor engineering arteris ip K. Charles Janac charlie janac noc interconnect ML/AI 5G cyber security

Join the Arteris IP Team in Silicon Valley!

Featured Position!

Senior Software Engineering Manager in 
Campbell, CA


We are looking for an experienced Senior Software Engineering Manager who will report to the VP of Engineering. 

Our current product is powering the creation of the most advanced artificial intelligence, mobile phone, and self-driving car SoCs.

You, as a successful candidate, are dynamic and self motivated with excellent organizational, and technical skills who can effectively communicate across all levels of management.

Topics: software jobs ASIC design arteris ip noc interconnect job SoC designs C++ Java

Semiconductor Engineering: Safety Islands In Safety-Critical Hardware

 Arteris IP's Kurt Shuler, vice president of marketing, authored this latest article in Semiconductor Engineering, from a joint Arm, Arteris IP and Dream Chip presentation at Arm TechCon 2019:

Safety Islands In Safety Critical Hardware

November 7th, 2019 - By Kurt Shuler

Creating a reliable place to manage critical functions when a design contains a mix of ASILs.

 

Safety and security have certain aspects in common so it shouldn’t be surprising that some ideas evolving in one domain find echoes in the other. In hardware design, a significant trend has been to push security-critical functions into a hardware root-of-trust (HRoT) core, following a philosophy of putting all (or most) of those functions in one basket and watching that basket very carefully. A somewhat similar principle applies for safety islands in safety-critical designs, in this case a core which will continue to function safely under all possible circumstances. The objective is the same – a reliable center for managing critical behavior, though from there the implementation details diverge.

For more information on this presentation and to download, please go here; https://www.arteris.com/download-arm-techcon-implementing-iso-26262-compliant-ai-systems-on-chip-with-arm-arteris

Topics: SoC economics ARM ISO 26262 ASIL D semiconductor engineering arteris ip kurt shuler noc interconnect Dream Chip