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Semiconductor Engineering: Safety Islands In Safety-Critical Hardware

 Arteris IP's Kurt Shuler, vice president of marketing, authored this latest article in Semiconductor Engineering, from a joint Arm, Arteris IP and Dream Chip presentation at Arm TechCon 2019:

Safety Islands In Safety Critical Hardware

November 7th, 2019 - By Kurt Shuler

Creating a reliable place to manage critical functions when a design contains a mix of ASILs.

 

Safety and security have certain aspects in common so it shouldn’t be surprising that some ideas evolving in one domain find echoes in the other. In hardware design, a significant trend has been to push security-critical functions into a hardware root-of-trust (HRoT) core, following a philosophy of putting all (or most) of those functions in one basket and watching that basket very carefully. A somewhat similar principle applies for safety islands in safety-critical designs, in this case a core which will continue to function safely under all possible circumstances. The objective is the same – a reliable center for managing critical behavior, though from there the implementation details diverge.

For more information on this presentation and to download, please go here; https://www.arteris.com/download-arm-techcon-implementing-iso-26262-compliant-ai-systems-on-chip-with-arm-arteris

Topics: SoC economics ARM ISO 26262 ASIL D semiconductor engineering arteris ip kurt shuler noc interconnect Dream Chip

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Join the Arteris IP Team as a Corporate Application Engineer!

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Our current product is powering the creation of the most advanced artificial intelligence, mobile phone, and self-driving car SoCs.

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