Arteris Articles

SemiWiki: Safety and Platform-Based Design

Kurt Shuler, VP Marketing at Arteris IP, updates Bernard Murphy of SemiWiki on some of the ways that safety and platform-based design interact, particularly where fail-operational functionality is required in autonomous or semi-autonomous systems, in this new SemiWiki blog:

Safety and Platform-Based Design

October 22nd, 2019 - By Bernard Murphy

Platform-based design, an approach to easily support multiple derivatives, opens some interesting new twists for safety-centric design. 

Bernard was at Arm TechCon as usual this year and one of the first panels he covered was close to the kickoff, hosted by Andrew Hopkins (Dir System Technology at Arm), Kurt Shuler (VP Marketing at Arteris IP) and Jens Benndorf (Managing Dir and COO at Dream Chip Technologies). The topic was implementing ISO 26262-compliant AI SoCs with Arm and Arteris IP, highly relevant since more and more of this class of SoC are appearing in cars. One thing that really stood out for me was the value of platform-based design in this area, something you might think would be old news for SoC design but which introduces some new considerations when safety becomes important.

You can learn more about this design by downloading the Arm TechCon presentation HERE.

Topics: SoC ARM semiconductor automotive automotive functional safety ArterisIP ISO 26262 compliance artificial intelligence AI semiwiki kurt shuler noc interconnect AI SoCs ASIL compliance

Arteris IP is Presenting at The Linley Spring Processor Conference April 10 - 11, 2019!


Don't Miss the Arteris IP Presentation on AI SoC Architectures, Thursday, April 11, 2019 

Location: Hyatt Regency, Santa Clara, CA
Session 5: SoC Design: Thursday, April 11
1:15 pm - 2:45 pm

Arteris IP presenting: "Adapting SoC Architectures for Types of Artificial-Intelligence Processing"

Come to the Linley Spring Processor Conference on April 10 - 11, 2019  - and attend the Arteris IP presentation on Thursday, April 11 during Session 5: SoC Design, were we will describe lessons learned on how to use network-on-chip (NoC) technology to efficiently implement SoC architectures targeted for different types of AI processing, including advanced techniques like when to use tiling or cache coherence, whether for edge/battery-operated or datacenter chips. 

April 11 Agenda: https://www.linleygroup.com/events/agenda.php?num=46&day=2

Topics: NoC semiconductor ArterisIP artificial intelligence SoCs edge/battery-operated cache coherence datacenter chips

Forbes Technology Council: AI and the Third Wave of Silicon Processors

Ty Garibay, CTO at Arteris IP, authors this article for Forbes Technology Council:

Topics: interconnect IP Systems-on-Chip ArterisIP flexnoc interconnect AI GPUs ips Forbes

Semiconductor Engineering: New Shifts In Automotive Design

Kurt Shuler, vice president of marketing at ArterisIP said, “Oh, you changed the software, you changed the system. Now you’ve got to have that car go and get certified to get running through that track all by itself” in this Semiconductor Engineering article:

New Shifts In Automotive Design

 

April 5th, 2018 - By Ann Steffora Mutschler

Topics: functional safety SoC security autonomous vehicles automotive functional safety ArterisIP neural networks ISO 26262 compliance NoC technology semiconductor engineering mesh