Arteris Articles

Arteris and Synopsys Webinar Held on Wednesday, 26 September

synopsys_color_600pxHolger Keding (Synopsys' Solutions Architect), Rocco Jonack (Arteris' Senior Solutions Architect) and Malte Doerper (Synopsys' Product Marketing) will be jointly hosting this webinar,
"Optimization of Cache Coherent Interconnects for Artificial Intelligence SoCs",
on Wednesday, 26 September, at 10 am Pacific time.

Topics: Synopsys cache coherent interconnect artificial intelligence SoCs webinar architect

IEEE Electronics 360: How to Efficiently Achieve ASIL-D Compliance Using NoC Technology

Learn from the experts at Arteris IP in this new White Paper:

How to Efficiently Achieve ASIL-D Compliance Using NoC Technology

 

 

 

Topics: arteris ip semiconductor interconnects artificial intelligence ASIL D ISO 26262 compliance soc designers ADAS functional safety automotive aerospace aeronautics LED latency SoC economics kurt shuler Z01X Synopsys Austemper

Semiconductor Engineering: Architecting for AI

Ty Garibay, CTO at Arteris IPparticipated on the "Experts at the Table" at DAC with other industry luminaries for this Semiconductor Engineering article:

Architecting for AI

 

July 7th, 2018 - By Ann Steffora Mutschler

Topics: semiconductor engineering arteris ip semiconductor interconnects artificial intelligence machine learning inference thermal envelope constraints power efficiency

Architecting the Future of Deep Learning

Ty Garibay, CTO of Arteris IP, delivered the Keynote Address, “Architecting the Future of Deep Learning," which discusses the emerging system-on-chip (SoC) architectures enabling artificial intelligence, machine learning, and deep learning and how semiconductor technology can enable these innovations. Ty presented this keynote presentation at the eSilicon ASICs Unlock Deep Learning Innovation Seminar on March 14, 2018.

Topics: eSilicon deep learning machine learning artificial intelligence soc architecture