Arteris Articles

Semiconductor Engineering: Variables Complicate Safety-Critical Device Verification

Kurt Shuler, Vice President of Marketing at Arteris IP participates in this new "Experts at the Table" article in Semiconductor Engineering:

Variables Complicate Safety-Critical Device Verification 

July 1st, 2020 - By Ann Steffora Mutschler

What's the best way to approach designs like AI chips for automotive that can stand the test of time? 

 
SE: Where does the industry stand with the task of verifying safety-critical devices today?
 
Kurt Shuler responds, "At the chip level we still have a situation where the verification people and methodologies are separate from the functional safety people and methodologies. This results in some overlap and rework. As tools and data interchange standards (like IEEE P2851 being led by both IEEE and Accellera) mature, we’ll be able to have more automation where functional safety validation through fault injection can be executed as part of regular verification processes. This will help everyone in the industry have more confidence that products don’t regress in diagnostic coverage as new versions are developed and will provide integrators/users of safety-critical systems to more easily perform fault injection validation of safety mechanisms if they desire."
 
Topics: SoC ISO 26262 automotive NoC technology semiconductor engineering ASIL D AI chips noc interconnect IP market IEEE P2851 fault injection

SemiWiki: AI, Safety and Low Power, Compounding Complexity

Bernard Murphy talked to Kurt Shuler about the complexities of combining low power, safety and AI constraints in a design. Design challenges have evolved beyond PPA to encompass new constraints but these are still manageable, with the right architecture in this new SemiWiki blog:

AI, Safety and Low Power, Compounding Complexity 

April 28th, 2020 - By Bernard Murphy

The nexus of complexity in SoC design these days has to be in automotive ADAS devices. Arteris IP highlighted this in the Linley Processor Conference recently where they talked about an ADAS chip that Toshiba had built. This has multiple vision and AI accelerators, both DSP and DNN-based. It is clearly aiming for ISO 26262 ASIL D certification since the design separates a safety island from the processing island, pretty much the only way you can get to ASIL D in a heterogenous mix of ASIL-level on-chip subsystems. Equally clear, it’s aiming to run at low power – around 2.7W for the processing island (the bulk of the functionality). It’s all very well to be smart but when you have dozens of smart components scattered around the car, that adds up to a lot of power consumption. The car isn’t going to be very smart if it runs its battery flat.

 

Topics: SoC ISO 26262 semiconductor Toshiba ADAS Ncore FlexNoC AI semiwiki ASIL D noc interconnect memory hierarchy

IEEE Electronics 360: How to Efficiently Achieve ASIL-D Compliance Using NoC Technology

Learn from the experts at Arteris IP in this new White Paper:

How to Efficiently Achieve ASIL-D Compliance Using NoC Technology

 

 

 

Topics: SoC economics Synopsys functional safety semiconductor automotive ADAS ISO 26262 compliance artificial intelligence arteris ip latency ASIL D interconnects soc designers aerospace aeronautics LED kurt shuler Z01X Austemper

Design & Reuse: Interconnect for AI and Automotive Solutions Video

Kurt Shuler, VP of Marketing at Arteris IP, discusses AI and Automotive in this video:

Design & Reuse: Arteris IP Interconnect for AI and Automotive Solutions 

June 26th, 2018 

Gabrielle interviews Kurt Shuler at DAC 2018, San Francisco, CA

Topics: ADAS autonomous vehicles ISO 26262 training FlexNoC ISO 26262 compliance ISO 26262 certification ISO 26262 specification ASIL D safety functional safety manager