Arteris Articles

SystemC Gurus Wanted! Arteris IP is Hiring Performance Modeling Engineers

Featured Position!

Performance Modeling Engineer
in Campbell, CA or Austin, TX

Would you like to be part of a team contributing to products that will be used in the next-generation of advanced smartphones, automobiles and other computing devices?

Topics: AXI OCP ASIC design cache coherency system level modeling SystemC arteris ip SoCs noc interconnect job

Arteris IP is Hiring!

Performance Modeling Engineer
in Campbell, CA or Austin, TX

Would you like to be part of a team contributing to products that will be used in the next-generation of advanced smartphones, automobiles and other computing devices?

Topics: AXI OCP ASIC design cache coherency arteris ip hardware SoCs noc interconnect job

IP Transaction Protocols: Plug and Play AMBA, OCP and others

As engineers, we view transaction protocols as simply a language to be able to communicate information from one block of system-on-chip (SoC) IP to another block. However, if you look at transaction protocols from an economics framework you see there’s much more to it. With the past interconnect fabrics dominated by crossbars and hierarchal busses, the choice of the IP transaction protocol created a humongous switching cost.

Topics: protocol IP protocols interconnect fabric NoC AMBA AHB AXI OCP transaction protocols

MIPI LLI Webinar on EE Times, Wednesday, 27 June

Hezi Saar (Synopsys' M-PHY PM), Philippe Martin (Arteris Senior Fellow and LLI God) and I will be hosting an EE Times webinar on the MIPI Low Latency Interface (MIPI LLI) and M-PHY on Wednesday, 27 June, at 9 am Pacific time.

Topics: Synopsys AXI MIPI LLI M-PHY