Arteris Articles

Arteris IP at DVCon 2019 Silicon Valley

Arteris IP at DVCon U.S. 2019 

Location: DoubleTree Hotel, 2050 Gateway Place, San Jose, CA
Poster Sessions: Tuesday, 26 February, 10:30am - 12:00pm, Gateway Foyer, 2nd level

Arteris IP is presenting the poster, "4.8 Flex-Checker: A One Stop Shop for all your Checkers: A Methodology for Elastic Score-boarding"

Topics: NoC semiconductor noc interconnect SoCs bandwidth latency performance hardware verification

Semiconductor Engineering: More Nodes, New Problems

Benny Winefeld, solutions architect at Arteris IP, adds additional commentary to this Semiconductor Engineering article:

More Nodes, New Problems

 

April 26th, 2018 - By Ann Steffora Mutschler

Topics: semiconductor engineering neural networks NoC technology SoC design latency bandwidth arteris ip Soft IP