Arteris Articles

SemiWiki: A Last-Level Cache for SoCs

JP Loison, Senior Corporate Application Architect at Arteris IP, chats with Bernard Murphy in this SemiWiki blog:

A Last-Level Cache for SoCs  

July 19th,  2018 - By Bernard Murphy

Based on a discussion with JP Loison, Bernard Murphy (SemiWiki) describes Arteris IP’s latest IP introduction - a last-level cache (LLC) for use outside the coherent domain, for accelerators and other IP that can benefit from cache support. He also touches on benefits offered by significant flexibility in adapting the IP for different use-models.

Topics: SoC semiwiki CodaCache cache on-chip memory CPU performance multi-processor systems Ncore cache coherent IP last level cache scratchpad way partitioning congestion configurability

Semiconductor Engineering: Power Optimization Strategies Widen

Benoit de Lescure, Sr. Director of Technology at Arteris IP, quoted in this Semiconductor Engineering article:

Power Optimization Strategies Widen

 

May 10th, 2018 - By Brian Bailey

Topics: semiconductor engineering arteris ip low power cache car external memory complex doc ADAS systems