Arteris Articles

SemiWiki: A Last-Level Cache for SoCs

JP Loison, Senior Corporate Application Architect at Arteris IP, chats with Bernard Murphy in this SemiWiki blog:

A Last-Level Cache for SoCs  

July 19th,  2018 - By Bernard Murphy

Based on a discussion with JP Loison, Bernard Murphy (SemiWiki) describes Arteris IP’s latest IP introduction - a last-level cache (LLC) for use outside the coherent domain, for accelerators and other IP that can benefit from cache support. He also touches on benefits offered by significant flexibility in adapting the IP for different use-models.

Topics: SoC semiwiki CodaCache cache on-chip memory CPU performance multi-processor systems Ncore cache coherent IP last level cache scratchpad way partitioning congestion configurability

SemiEngineering: Memory Choices Grow

Editor's note: This is a great article by Ed Sperling at Semiconductor Engineering, so I have highlighted it here. Cache coherency in modern SoCs is discussed toward the middle of the article. -Kurt

Read the entire article at Semiconductor Engineering.


Memory Choices Grow

Memory is emerging as the starting point for SoCs, adding more confusion to already complex designs.

NOVEMBER 24TH, 2015 - BY: ED SPERLING

Memory is becoming one of the starting points for SoC architectures, evolving from a basic checklist item that was almost always in the shadow of improving processor performance or lowering the overall power budget. In conjunction with that shift, chipmakers must now grapple with many more front-end decisions about placement, memory type and access prioritization.

Topics: cache coherent IP memory