Arteris Articles

All About Circuits: The Role of Last-Level Cache Implementation for SoC Developers

Kurt Shuler, vice president of marketing at Arteris IP authored this new All About Circuits article:

The Role of Last-Level Cache Implementation for SoC Developers

May 13th, 2020 - By Kurt Shuler

There is a challenge for SoC developers to find ways to navigate the demand of memory in their design. This article looks at how a fourth, or last-level, cache can provide a solution.

So, what’s the best memory solution? For hints, we can look at what other companies are doing. Tear-down analyses have shown that Apple, for one, solves the speed mismatch problem by adding another cache. If a big company with nearly infinite R&D resources designs around its SoCs bottlenecks this way, it’s probably worth looking into. 
 
Topics: Apple SoC NoC technology CodaCache last level cache kurt shuler noc interconnect ML IP market security All About Circuits DSP

Semiconductor Engineering: Last-Level Cache Video

Tech Talk Video: Last-Level Cache 

April 6th, 2020 - By Ed Sperling

Kurt Shuler, vice president of marketing at Arteris IP, explains how to reduce latency and improve performance with last-level cache in order to avoid sending large amounts of data to external memory, and how to ensure quality of service on a chip by taking into account contention for resources.

Topics: network-on-chip semiconductor CodaCache tech talk video on-chip memory data centers memory hierarchy semiengineering

Semiconductor Engineering: AI, Performance, Power, Safety Shine Spotlight on Last-Level Cache

Kurt Shuler, vice president of marketing at Arteris IP writes about overcoming memory limitations in automotive systems in this Semiconductor Engineering article:

AI, Performance, Power, Safety Shine Spotlight on Last-Level Cache

April 2nd, 2020 - By Kurt Shuler

Memory limitations to performance, always important in modern systems, have become an especially significant concern in automotive safety-critical applications making use of AI methods. On one hand, detecting and reporting a potential collision or other safety problem has to be very fast. Any corrective action is constrained by physics and has to be taken well in advance to avoid the problem.
 
Topics: SoC automotive NoC technology semiconductor engineering CodaCache performance last level cache noc interconnect IP market

SemiWiki: A Last-Level Cache for SoCs

JP Loison, Senior Corporate Application Architect at Arteris IP, chats with Bernard Murphy in this SemiWiki blog:

A Last-Level Cache for SoCs  

July 19th,  2018 - By Bernard Murphy

Based on a discussion with JP Loison, Bernard Murphy (SemiWiki) describes Arteris IP’s latest IP introduction - a last-level cache (LLC) for use outside the coherent domain, for accelerators and other IP that can benefit from cache support. He also touches on benefits offered by significant flexibility in adapting the IP for different use-models.

Topics: SoC cache coherent IP CPU Ncore semiwiki cache CodaCache on-chip memory performance multi-processor systems congestion configurability last level cache scratchpad way partitioning