Arteris Articles

SemiWiki: A Last-Level Cache for SoCs

JP Loison, Senior Corporate Application Architect at Arteris IP, chats with Bernard Murphy in this SemiWiki blog:

A Last-Level Cache for SoCs  

July 19th,  2018 - By Bernard Murphy

Based on a discussion with JP Loison, Bernard Murphy (SemiWiki) describes Arteris IP’s latest IP introduction - a last-level cache (LLC) for use outside the coherent domain, for accelerators and other IP that can benefit from cache support. He also touches on benefits offered by significant flexibility in adapting the IP for different use-models.

Topics: SoC semiwiki CodaCache cache on-chip memory CPU performance multi-processor systems Ncore cache coherent IP last level cache scratchpad way partitioning congestion configurability

CES 2016: CPU, GPU or … VPU?

Winners, losers and observations from the Consumer Electronics Show

Where is the semiconductor industry going in the post-smartphone era? What trends are going to shape next-generation applications and SoC development?

Just by walking around the CES show floor this year, I would say advanced visual processing technology is the horse to put money on. It was everywhere, from ADAS systems, drones, to GoPro cameras, IP cameras with embedded facial recognition, motion detectors, virtual reality, augmented reality, displays and a whole lot more.

Topics: automotive semiconductors ADAS CPU GPU video