Arteris Articles

Semiconductor Engineering: Interconnect Challenges Grow, Tools Lag

Benoit de Lescure, CTO at Arteris IP comments in this new Semiconductor Engineering article:

Interconnect Challenges Grow, Tools Lag 

June 15th, 2020 - By Brian Bailey

More data, smaller devices are hitting the limits of current technology. The fix may be expensive. 
 
Chips are growing. “Ten years ago, the interconnect would be concerned with about 10K gates,” says Benoit de Lescure, CTO for Arteris IP. “Now they need to interconnect 10M gates on a chip, so there’s been a very significant increase in complexity. The number of clients on the interconnect has increased.”
 
Topics: SoC NoC technology semiconductor engineering Benoit de Lescure CTO broadcast noc interconnect ai accelerators IP market networking chips multicast

Semiconductor Engineering: Adding NoCs To FPGA SoC

Ty Garibay, CTO at Arteris IP, comments on Bridging the gap:

Adding NoCs To FPGA SoCs 


June 28th,  2018 - By Ann Steffora Mutschuler

As complexity and device sizes rise, so does the need for an on-chip network.

Topics: NoC functional safety FPGA FlexNoC Ty Garibay arteris ip hardware SoCs SerDes digital 100-gigabit HBM2 CTO