Arteris Articles

Semiconductor Engineering: Safety Islands In Safety-Critical Hardware

 Arteris IP's Kurt Shuler, vice president of marketing, authored this latest article in Semiconductor Engineering, from a joint Arm, Arteris IP and Dream Chip presentation at Arm TechCon 2019:

Safety Islands In Safety Critical Hardware

November 7th, 2019 - By Kurt Shuler

Creating a reliable place to manage critical functions when a design contains a mix of ASILs.

 

Safety and security have certain aspects in common so it shouldn’t be surprising that some ideas evolving in one domain find echoes in the other. In hardware design, a significant trend has been to push security-critical functions into a hardware root-of-trust (HRoT) core, following a philosophy of putting all (or most) of those functions in one basket and watching that basket very carefully. A somewhat similar principle applies for safety islands in safety-critical designs, in this case a core which will continue to function safely under all possible circumstances. The objective is the same – a reliable center for managing critical behavior, though from there the implementation details diverge.

For more information on this presentation and to download, please go here; https://www.arteris.com/download-arm-techcon-implementing-iso-26262-compliant-ai-systems-on-chip-with-arm-arteris

Topics: SoC economics ARM ISO 26262 ASIL D semiconductor engineering arteris ip kurt shuler noc interconnect Dream Chip

Wake Up, Semi Industry: System OEMs Might Not Need You

The rules are changing for the semiconductor industry and traditional vendors had better find ways to be more competitive or they will find themselves missing out on some of the most exciting, high-growth markets.

Topics: semiconductor industry economics semiconductor industry economics OEM

Advanced SoC Interconnect IP Enables Greater Flexibility in an Era of Consolidation

I am thoroughly enjoying 2013. That’s because there seems to be a lot more reason for optimism this year than last year.  But before we let go of 2012, it’s important to reflect on the past year and see what it can teach us so we can make better business decisions moving forward.

Topics: semiconductor industry SoC economics IP economics intellectual property semiconductor industry economics NoC software network-on-chip network-on-chip research ASICs ASIC design FPGAs field programmable gate arrays FPGA design cores on-chip interconnect

The Gartner Hype Cycle & Technology Adoption Lifecycle Explained (using NoC Technology)

My purpose in this article is to explain Gartner Research’s Hype Cycle and relate it to the Technology Adoption Lifecycle popularized by Geoffrey Moore’s book, “Crossing the Chasm.”  These two models can be used together to provide a combined picture of market expectations and expected technology adoption rates, but people often get the timeframes and takeaways wrong. So if you’re involved in technology as an engineer, marketer or manager, read on!

Topics: semiconductor industry economics network-on-chip research Gartner