Arteris Articles

Arteris IP at Synopsys Users Group Silicon Valley 2019


Arteris IP at SNUG Silicon Valley 2019 

Location: Santa Clara Convention Center, 5001 Great America Parkway, Santa Clara, CA  
Track: Artificial Intelligence - Wednesday, 20 March, 3:45 pm - 4:30 pm

Arteris IP is presenting this paper, "Using Machine Learning for Characterization of NoC Components"

Topics: NoC semiconductor FlexNoC Soft IP SoCs RTL noc interconnect ML PPA

SemiWiki: On-Chip Networks at the Bleeding Edge of ML

On-chip networks become a lot more challenging at the high-end of machine learning (ML). Bernard Murphy (SemiWiki) talked with Kurt Shuler, VP Marketing at Arteris IP, about the experience they have developed over the years of working with well-known ML product builders and how this has influenced  the AI package recently released by Arteris IP in this SemiWiki blog:

On-Chip Networks at the Bleeding Edge of ML 

November 29th,  2018 - By Bernard Murphy

I wrote a while back about some of the more exotic architectures for machine learning (ML), especially for neural net (NN) training in the data center but also in some edge applications. In less hairy applications, we’re used to seeing CPU-based NNs at the low end, GPUs most commonly (and most widely known) in data centers as the workhorse for training, and for the early incarnations of some mobile apps (mobile AR/MR for example), FPGAs in applications where architecture/performance becomes more important but power isn’t super-constrained, DSPs in applications pushing performance per watt harder and custom designs such as the Google TPU pushing even harder.

Topics: SoC NoC FPGAs semiconductor machine learning FlexNoC semiwiki kurt shuler AI chips flexnoc ai package

Arm and Arteris IP present AI NPU and ISO 26262 integration together at ICCAD China

On Friday, Jerry Shu, Senior Manager for Automotive Marketing at Arm and Gary Ge, Senior Solutions Architect at Arteris IP, jointly presented "Implementing ISO 26262 Compliant AI Systems with Arm and Arteris IP" to an audience at the ICCAD China conference in Zhuhai China.

Topics: ISO 26262 FlexNoC AI AI chips Arm Cortex Arm NPU

ElectronicDesign Article: Speed Machine-Learning Accelerators with Flexible Interconnect


This ElectronicsDesign article, 'Speed Machine-Learning Accelerators with Flexible Chip Interconnect', covers the announcement of Arteris IP's new FlexNoc with AI Package in this interview with Kurt Shuler, VP Marketing at Arteris IP. 

November 1 , 2018 - By William Wong

Topics: autonomous vehicles FlexNoC AI SoCs AI chips OEMs noc multicast torus noc broadcast VC-Links