Arteris Articles

SemiWiki: Why High-End ML Hardware Goes Custom

Kurt Shuler, VP Marketing at Arteris IP,  provides more insight into what's happening in this highly dynamic space in the latest SemiWiki blog written by Bernard Murphy (SemiWiki):

Why High-End ML Hardware Goes Custom

January 30th, 2019 - By Bernard Murphy

In a hand-waving way it’s easy to answer why any hardware goes custom (ASIC): faster, lower power, more opportunity for differentiation, sometimes cost though price isn’t always a primary factor. But I wanted to do a bit better than hand-waving, especially because these ML hardware architectures can become pretty exotic, so I talked to Kurt Shuler, VP Marketing at Arteris IP, and I found a useful MIT tutorial paper on arXiv. Between these two sources, I think I have a better idea now.

Start with the ground reality. Arteris IP has a bunch of named customers doing ML-centric design, including for example Mobileye, Baidu, HiSilicon and NXP. Since they supply network on chip (NoC) solutions to those customers, they have to get some insight into the AI architectures that are being built today, particularly where those architectures are pushing the envelope. What they see and how they respond in their products is revealing.

You can learn more about what Arteris IP is doing to support AI in these leading-edge ML design teams HERE. They certainly seem to be in a pretty unique position in this area.

 For more information, download this FlexNoC AI Package datasheet; http://www.arteris.com/flexnoc-ai-package

Topics: NoC semiconductor semiwiki kurt shuler AI chips flexnoc ai package accelerators noc interconnect ML-centric design

Semiconductor Engineering: Chasing Reliability In Automotive Electronics

 Arteris IP's Kurt Shuler, vice president of marketing has authored a paper about ISO 26262 and comments in this article;

Chasing Reliability In Automotive Electronics 

January 15th,  2019 - By Susan Rambo and Ed Sperling

Supply chain changes, resistance to sharing data and technology unknowns add up to continued uncertainty.

"Traditional semiconductor vendors who are making or designing chips to enable autonomous driving applications are nowadays sometimes competing with Tier-1 electronics system designers and OEMs, who may be making their own chips or providing explicit requirements to their semiconductor vendor partners. Additionally, new entrants like Uber, Way and Apple are designing their own complete systems, despite their relative lack of experience in the automotive industry. ISO 26262 mandates high levels of collaboration and information sharing throughout the value chain that may be unfamiliar to new entrants."

The ISO 26262 standard is snapshot of issues and the lengths the whole supply chain has to go. Collaboration is key. Communication is part of the safety standards up and down the automotive safety critical supply chain now. It’s built into the standards.

Sharing knowledge of a supplier’s crown jewels—intellectual property—has to happen among suppliers and auto OEMs. “Participants in the semiconductor and software supply chains are usually secretive about how their IP was developed and how it works in detail,” said Shuler. Suppliers should remember that the “your customer still has an obligation to confirm your compliance with ISO 26262.”

To learn more, please download this technical paper, Fundamentals of Semiconductor ISO 26262 Certification: People, Process and Product.

Topics: semiconductor automotive neural networks ISO 26262 certification AI AI chips flexnoc ai package noc interconnect ML AI SoC Designers

Semiconductor Engineering: AI Chips: NoC Interconnect IP Solves Three Design Challenges

 Arteris IP's Kurt Shuler warns that regular topologies, large chips, and huge bandwidths are considerations in AI-centric chips in the date center.

AI Chips: NoC Interconnect IP Solves Three Design Challenges  

January 10th,  2019 - By Kurt Shuler

New network-on-chip (NoC) interconnect IP is now available for artificial intelligence (AI) systems-on-chip (SoC). Arteris IP launched the fourth generation of FlexNoC interconnect IP with a new AI package.

The new NoC technology benefits emerging AI chip architectures in three main ways: automatically generating regular topologies, effectively managing the data flows of large chips with long wires and enabling large on- and off-chip bandwidths.

To learn more, please visit the FlexNoC AI Package page; https://www.arteris.com/flexnoc-ai-package and the Resources page: https://www.arteris.com/resources

Topics: semiconductor automotive neural networks AI AI chips flexnoc ai package VC-Links noc interconnect ML AI SoC Designers synchronous virtual channels

SemiWiki: Disturbances in the AI Force

Bernard Murphy (SemiWiki) reflects on a discussion with Kurt Shuler, VP Marketing at Arteris IP, on customer trends in design for advanced ML accelerators, why these look quite different from traditional processor architectures and the implication for design particularly around the NoC interconnect in this SemiWiki blog:

Disturbances in the AI Force

January 3rd, 2019 - By Bernard Murphy

In the normal evolution of specialized hardware IP functions, initial implementations start in academic research or R&D in big semiconductor companies, motivating new ventures specializing in functions of that type, who then either build critical mass to make it as a chip or IP supplier (such as Mobileye - initially) or get sucked into a larger chip or IP supplier (such as Intel or ARM or Synopsys). That was where hardware function ultimately settled, and many still do.

But recently the gravitational pull of mega-companies has distorted this normally straightforward evolution. In cloud services this list includes Amazon, Microsoft, Baidu and others. In smartphones you have Samsung, Huawei and Apple - yep, Huawei is ahead of Apple in smartphone shipments and is gunning to be #1. These companies, neither semiconductor nor IP, are big enough to do whatever they want to grab market share. What they do to further their goals in competition with the other giants can have a major impact on the evolution path for IP suppliers.

Arteris IP is closely involved with many of these companies, from Cambricon to Huawei/HiSilicon to Baidu to emerging companies like Lynxi, offering their network on chip (NoC) solutions with the AI package allowing for architecture tuning to the special needs of high-end NN designs. Check out more here; http://www.arteris.com/flexnoc-ai-package

Topics: NoC semiconductor semiwiki kurt shuler AI chips flexnoc ai package hardware ip accelerators noc interconnect