Arteris Articles

EE Times article, "Who's Who in AI SoCs," highlights Arteris IP

This EE Times article, "Who's Who in AI SoCs", highlights Arteris IP's role in artificial intelligence (AI) and machine learning (ML) chips in this interview with Kurt Shuler, VP Marketing at Arteris IP. 

November 1, 2018 - by Junko Yoshida

Topics: eetimes FlexNoC AI automotive design SoCs AI chips OEMs noc multicast DNN broadcast

Design & Reuse: Interconnect for AI and Automotive Solutions Video

Kurt Shuler, VP of Marketing at Arteris IP, discusses AI and Automotive in this video:

Design & Reuse: Arteris IP Interconnect for AI and Automotive Solutions 

June 26th, 2018 

Gabrielle interviews Kurt Shuler at DAC 2018, San Francisco, CA

Topics: ADAS autonomous vehicles ISO 26262 training FlexNoC ISO 26262 compliance ISO 26262 certification ISO 26262 specification ASIL D safety functional safety manager

Semiconductor Engineering: 7nm Design Challenges Video

Tech Talk: Why the next nodes will be so expensive, and how they will play out in chip design.

Tech Talk Video: 7nm Design Challenges 

July 9th,  2018 - By Ed Sperling

Ed Sperling interviews Ty Garibay, CTO at Arteris IP headquarters about the challenges of moving to 7nm, who’s likely to head there, how long it will take to develop chips at that node, and why it will be so expensive. This also raises questions about whether chips will begin to disaggregate at 7nm and 5nm.

Topics: FlexNoC safety tech talk video 7nm

Semiconductor Engineering: Adding NoCs To FPGA SoC

Ty Garibay, CTO at Arteris IP, comments on Bridging the gap:

Adding NoCs To FPGA SoCs 


June 28th,  2018 - By Ann Steffora Mutschuler

As complexity and device sizes rise, so does the need for an on-chip network.

Topics: NoC functional safety FPGA FlexNoC Ty Garibay arteris ip hardware SoCs SerDes digital 100-gigabit HBM2 CTO