Arteris Articles

SemiWiki: Segmenting the Machine-Learning Hardware Market

Kurt Shuler, VP Marketing at Arteris IP, shares his 91 entries into finding every company and product that is active in the AI hardware space in this latest SemiWiki blog:

Segmenting the Machine-Learning Hardware Market

March 13th, 2019 - By Bernard Murphy

Machine learning is everywhere, but it can be difficult at times to understand what that really means. Bernard Murphy (SemiWiki) talked to Kurt Shuler and dug through a very detailed spreadsheet Kurt developed to understand better better what is being used where in the ML market.

One of the great pleasures in what I do is to work with people who are working with people in some of the hottest design areas today. A second-level indirect to be sure but that gives me the luxury of taking a broad view. A recent discussion I had with Kurt Shuler (VP Marketing at Arteris IP) is in this class. As a conscientious marketing guy, he wants to understand the available market in AI hardware because they have quite a bit of activity in that space – more on that later. So Kurt put a lot of work into finding every company and product he could that is active in this space, 91 entries in his spreadsheet. This he broke down by company, territory (eg China or US), product, target market (eg vision or speech), implementation (eg FPGA or ASIC), whether the product is used in datacenters or at the edge and whether it is being used for training or inference. 


 For more information, download this FlexNoC AI Package datasheet; http://www.arteris.com/flexnoc-ai-package

Topics: FPGA semiconductor edge computing semiwiki inference kurt shuler flexnoc ai package AI training noc interconnect

Arteris IP at DATE 2019

Arteris IP at DATE 2019 

Location: Firenze Fiera, Florence, Italy
3.1 Executive Session 2: Panel
Date:
Tuesday, 26 March 2019
Time: 14:30 - 16:00
Location: Room 1

Arteris IP's CEO, K. Charles Janac joins this Executive Panel Session, "Semiconductor IP, Surfing the Next Big Wave"

Topics: FPGA semiconductor Soft IP SoCs noc interconnect hard ip

Semiconductor Engineering: Adding NoCs To FPGA SoC

Ty Garibay, CTO at Arteris IP, comments on Bridging the gap:

Adding NoCs To FPGA SoCs 


June 28th,  2018 - By Ann Steffora Mutschuler

As complexity and device sizes rise, so does the need for an on-chip network.

Topics: NoC functional safety FPGA FlexNoC Ty Garibay arteris ip hardware SoCs SerDes digital 100-gigabit HBM2 CTO

Is An FPGA IP Business Model Finally Possible?

As featured in:
The IP-SoC conference panel, “IPs on FPGA: Strategy and Vision,” was a learning experience for me. Coming from the software and silicon/ASIC/ASSP worlds, I thought I had a pretty comprehensive view of all the various IP licensing models and their technical implementations. But I learned something new that makes me feel positive about the FPGA’s abilities to finally offer a robust market of third party IP. 

Topics: IP Interconnect economics FPGA