Arteris Articles

Semiconductor Engineering: AI: Where's The Money?

 Arteris IP's Kurt Shuler, Vice President of Marketing, authored this article in Semiconductor Engineering about Artificial Intelligence (AI), and asks what is hype and what is reality?

AI: Where's The Money?

March 7th, 2019 - By Kurt Shuler

What the market for AI hardware might look like in 2025.

A one-time technology outcast, Artificial Intelligence (AI) has come a long way. Now there's groundswell of interest and investment in products and technologies to deliver his performance visual recognition, matching or besting human skills. We're overwhelmed by possibilities, but what is often less clear is where the money is really going. What is aspiration, what is hype and what is reality?

There are multiple ways to slice this question, such as dividing by applications or implementation choices. At Arteris IP, we have a unique view because our interconnect technology is used in many custom AI designs which, as we’ll see, are likely to dominate the space. Combining this view with recent McKinsey analyses provides some interesting and, in some cases, surprising insights.

Bottom line: AI is big, but there is no such thing as a “standard AI chip.” Optimal chip architectures differ according to the types of functions that must be executed, where they must be performed, and within what amount of time and power budget.

For more information on AI, please click on the Arteris FlexNoC AI Package webpage: http://www.arteris.com/flexnoc-ai-package.

Topics: SoC functional safety automotive semiconductor engineering AI noc interconnect chip architectures datacenters

Semiconductor Engineering: How To Build An Automotive Chip

 Arteris IP's Kurt Shuler, Vice President of Marketing, comments about the claims of technical safety requirements in this Semiconductor Engineering article;

How To Build An Automotive Chip

March 7th, 2019 - By Ann Steffora Mutschler

Changing standards, stringent requirements and a mix of expertise make this a tough marketing to crack.

IP issues
“One of the things that all of these guys deal with is having evidence that the specifications are being followed, both from a process standpoint of how the IP is designed,” said Kurt Shuler, vice president of marketing at Arteris IP. “And then, does the IP meet the technical safety requirements that are being claimed?”

This requires the IP customer to look closely at their different IP providers. “If I’m licensing some IP, I want to understand in pre-sales what do you have, how did you build it,” said Shuler. “What evidence and work products do you have to prove any claims that you make? Things may go quiet for a while until the design team gets closer to the end of the chip design project and starts doing the work where they have to calculate the diagnostic coverage and FMEDA, maybe some fault injection to validate, some of the assumptions they make in the FMEDA, among other activities.”

“If our customer or prospect has somebody who doesn’t understand functional safety or the specification, and is just going blindly through a checklist, it slows things down,” Shuler said. “So the right subject matter experts must be there.”

For more information about ISO 26262:2018 Part 11, please download this presentation "Fundamentals of ISO 26262 Part 11 for Semiconductors".

Topics: SoC functional safety ISO 26262 automotive semiconductor engineering AI RTL noc interconnect ML/AI

EE Times Designlines Blog: How to Not Fail ISO 26262

This EE Times blog in Designlines Automotive titled, How to Not Fail ISO 26262, is written by Kurt Shuler, VP Marketing at Arteris IP. 

Topics: functional safety ADAS eetimes mobileye ISO 26262 ASIL D tier 1 automotive design SoCs interconnects OEMs 3D mapping safety culture people process

EE Times Designlines Blog: Auto OEMs, Tier-Ones: Think SoC Designs

This EE Times blog in Designlines Automotive titled, Auto OEMs, Tier-Ones: Think SoC Designs, is written by Kurt Shuler, VP Marketing at Arteris IP. 

Topics: functional safety ADAS eetimes mobileye tier 1 automotive design LIDAR SoCs interconnects OEMs 3D mapping