Arteris Articles

EE Times Designlines Blog: How to Not Fail ISO 26262

This EE Times blog in Designlines Automotive titled, How to Not Fail ISO 26262, is written by Kurt Shuler, VP Marketing at Arteris IP. 

Topics: eetimes OEMs tier 1 automotive design ADAS SoCs 3D mapping mobileye functional safety interconnects ISO 26262 ASIL D safety culture people process

EE Times Designlines Blog: Auto OEMs, Tier-Ones: Think SoC Designs

This EE Times blog in Designlines Automotive titled, Auto OEMs, Tier-Ones: Think SoC Designs, is written by Kurt Shuler, VP Marketing at Arteris IP. 

Topics: eetimes OEMs tier 1 automotive design ADAS SoCs LIDAR 3D mapping mobileye functional safety interconnects

IEEE Electronics 360: How to Efficiently Achieve ASIL-D Compliance Using NoC Technology

Learn from the experts at Arteris IP in this new White Paper:

How to Efficiently Achieve ASIL-D Compliance Using NoC Technology

 

 

 

Topics: arteris ip semiconductor interconnects artificial intelligence ASIL D ISO 26262 compliance soc designers ADAS functional safety automotive aerospace aeronautics LED latency SoC economics kurt shuler Z01X Synopsys Austemper

Semiconductor Engineering: Not Enough Respect for SoC Interconnect

K. Charles Janac, CEO at Arteris IP, shares his opinion in this week's blog appearing in Semiconductor Engineering:

Not Enough Respect for SoC Interconnect

 

July 30th, 2018 - By K. Charles Janac

Topics: semiconductor engineering arteris ip SoC semiconductor interconnects logic flexnoc interconnect topologies ips IP modules SoC assembly advanced driver assistance systems adas K. Charles Janac AI on-chip memory 5G mobility soc architecture QoS functional safety SoC security