Arteris Articles

Semiconductor Engineering: In-System Networks Are Front And Center

 Arteris IP's Kurt Shuler, VP of Marketing, authored this article and offers his perspective on HotChips 2019 in this latest Semiconductor Engineering:

In-System Networks Are Front And Center

September 15th, 2019 - By Kurt Shuler

AI demands push innovation in design architectures and techniques.

 

This year’s HotChips conference at Stanford was all about artificial intelligence (AI) and machine learning (ML) and what particularly struck me, naturally because we’re in this business too, was how big a role on-chip networks played in some of the leading talks.

Giant leaps are being made in supporting new AI architectures, tuning them for optimum performance per milliwatt and embedding them effectively into traditional and novel SoC architectures.

You can learn more by reading my white paper titled, "Re-Architecting SoCs for the AI Era". Download is free; https://www.arteris.com/download-re-architecting-socs-for-the-ai-era

Topics: SoC functional safety ISO 26262 machine learning cache coherency semiconductor engineering AI kurt shuler noc interconnect SOTIF (ISO 21448 Hot Chips bigger chips

SemiWiki: AI, Safety and the Network

Kurt Shuler, VP Marketing at Arteris IP, and Bernard Murphy (SemiWiki) discuss, 'What is driving the boom in AI-centric design', in this new SemiWiki blog:

AI, Safety and the Network

September 4th, 2019 - By Bernard Murphy

You probably know that Arteris IP is very active in AI and safety, leveraging their central value in network-on-chip (NoC) architectures. Bernard Murphy of SemiWiki blogged on Kurt Shuler's front-to-back white-paper to walking us through the essentials of AI, particularly machine learning (ML) and its application for example in cars.

Kurt also highlights an interesting point about this rapidly evolving technology. As we build automation from the edge to the fog to the cloud, functionality, including AI, remains quite fluid between levels. Kurt points out that this is somewhat mirrored in SoC design. In both cases architecture is constrained by need to optimize performance and minimize power across the system through intelligent bandwidth allocation and data locality. And for safety-critical applications, design and verification for safety around intelligent features must be checked not only within and between SoCs in the car but also beyond, for example in V2x communication between cars and other traffic infrastructure.

You can learn more by downloading this Arteris IP white paper titled, Re-Architecting SoCs for the AI Era: https://semiwiki.com/automotive/274598-ai-safety-and-the-network/

Topics: SoC functional safety ISO 26262 semiconductor automotive ADAS machine learning artificial intelligence semiwiki kurt shuler flexnoc ai package noc interconnect

New! Arteris IP Technical Paper, Re-Architecting SoCs for the AI Era

Kurt Shuler, VP of Marketing at Arteris IP has written this 10-page technical paper titled, "Re-Architecting SoCs for the AI Era".

August 29, 2019 - by Kurt Shuler

Abstract:
The growth of artificial intelligence (AI) demands that semiconductor companies re-architect their system on chip (SoC) designs to provide more scalable levels of performance, flexibility, efficiency, and integration. From the edge to data centers, AI applications require a rethink of memory structures, the numbers and types of heterogeneous processors and hardware accelerators, and careful consideration of how the dataflow is enabled and managed between the various high-performance IP blocks.

Topics: functional safety ISO 26262 semiconductor machine learning autonomous driving artificial intelligence AI SoCs kurt shuler noc interconnect ML dataflow

Semiconductor Engineering: Edge Complexity To Grow For 5G

 Arteris IP's Kurt Shuler, Vice President of Marketing, quoted in the latest Semiconductor Engineering article:

Edge Complexity To Grow For 5G

July 2nd, 2019 - By Kevin Fogarty and Ed Sperling

Increased interdependence of technologies will drive different architectures and applications. 

It gets even more complicated in the automotive world than other any other markets because of safety-critical circuitry.

“You may have to reboot part of the chip for a failed operation, while keeping the rest of it operating in a safe state,” said Kurt Shuler, vice president of marketing at Arteris IP. “If you think about the space shuttle or a Boeing 777, the black boxes are 20 pounds. You can’t have that in a car. There is a lot of functional safety being done at the microprocessor level to save cost. That can be used to spy on what’s happening at the system level, so if there are problems you can isolate them and in a safe state and fail gracefully. If there is a transient error, you reboot.”

For more information, please download the Arteris FlexNoC AI Package data sheet; http://www.arteris.com/download-flexnoc-ai-package-datasheet

Topics: SoC functional safety FPGAs semiconductor engineering flexnoc ai package noc interconnect ML