Arteris Articles

Semiconductor Engineering: Big Shift In Multi-Core Design

 Arteris IP's Kurt Shuler, Vice President of Marketing, adds commentary in this article in Semiconductor Engineering.

Big Shift In Multi-Core Design

April 3rd, 2019 - By Ann Steffora Mutschler

System-wide concerns in AI and automotive are forcing hardware and software teams to work together, but gaps still remain.

Minding the gap
There are indications that mindset is beginning to change, particularly in markets such as automotive where systemic complexity extends well beyond a single chip or even a single vehicle.

“In the past, if you were a software engineer, the thinking was, ‘I have this chip available. Here’s what I can produce with my software,'” said Kurt Shuler, vice president of marketing at Arteris IP. “Nowadays, especially in the ADAS side of things that have an AI component or some kind of programmable object detection for the ADAS functionality, or an AI chip—whether it’s for the data center, edge, inference or training—the thinking has shifted more to system-design decisions. If this is designed with this given set of software algorithms, it is clear what needs to happen at a system level from the hardware and software point of view. At what level of detail should I optimize this hardware for the particular software I expect to run? This means the hardware and the software are now much more tightly integrated in those use cases than they probably have ever been unless it’s a very detailed embedded application. So now, in the early stages of design for these types of chips, whether it’s the autonomous driving chips or the AI chips, the software architect is in there, too.”

This is a definite sign of progress. “Before, they didn’t care,” Shuler said. “The layer/API between hardware and software is becoming less generic and more specific for those kinds of use cases, solving those kinds of problems. What that means, though, is there are software guys who went to Stanford and trained on Java script and have no idea what a register is. Then there are hardware guys who have no idea what a hypervisor or object-oriented programming is.”

For more information on AI, please click on the Arteris FlexNoC AI Package webpage: http://www.arteris.com/flexnoc-ai-package.

Topics: SoC software automotive ADAS autonomous driving semiconductor engineering AI hardware noc interconnect

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Semiconductor Engineering: Adding NoCs To FPGA SoC

Ty Garibay, CTO at Arteris IP, comments on Bridging the gap:

Adding NoCs To FPGA SoCs 


June 28th,  2018 - By Ann Steffora Mutschuler

As complexity and device sizes rise, so does the need for an on-chip network.

Topics: NoC functional safety FPGA FlexNoC Ty Garibay arteris ip hardware SoCs SerDes digital 100-gigabit HBM2 CTO