Arteris Articles

It’s Time to Stop Kicking the EDA Dog

It's incumbent on IP vendors to deliver higher quality designs that enable a smoother back-end process.

As SoC designers, we are usually insulated from the back-end of the chip design process. We don’t encounter the place and route and timing closure problems that must be resolved by others to turn our front-end logic designs into real chips. Those problems often create challenges that delay our project schedules and prevent us from bringing our chip to market in a timely fashion. To reverse these delays, the industry needs to do a better job of improving the front-end design so it can avoid problems in the back end.

Topics: hardware design place and route

Arteris is hiring engineers!

You may have noticed from the Arteris LinkedIn company page or our website that we have been hiring. We have three more jobs where we need top people:

Topics: hardware verification hardware design arteris jobs