Arteris Articles

Advanced SoC Interconnect IP Enables Greater Flexibility in an Era of Consolidation

I am thoroughly enjoying 2013. That’s because there seems to be a lot more reason for optimism this year than last year.  But before we let go of 2012, it’s important to reflect on the past year and see what it can teach us so we can make better business decisions moving forward.

Topics: NoC network-on-chip economics IP research semiconductor industry software SoC economics semiconductor industry economics ASICs ASIC design FPGAs field programmable gate arrays FPGA design intellectual property cores network-on-chip on-chip interconnect

MIPI LLI or C2C?

Two new options for interchip connectivity are available today that enable sharing a DRAM memory between two chips for data and programs. These standards, called MIPI Low Latency Interface (MIPI LLI) and Chip-to-Chip (C2C), are primarily targeted at mobile phones, where a mobile phone’s modem usually requires its own discreet DRAM. With either C2C or MIPI LLI, the mobile phone modem can use the application processor’s DRAM though a low-latency, memory-mapped connection that requires no software drivers or runtime software.

Topics: IP C2C LLI interchip connectivity MIPI LLI

TI OMAP 5 Platform includes MIPI LLI and C2C interchip connectivity

TI has placed extensive information on their new OMAP5430 and OMAP5432 processors on their web page:  http://www.ti.com/ww/en/omap/omap5/omap5-OMAP5430.html

Topics: SoC IP TI OMAP 5 platform C2C Chip to Chip LLI OMAP

Is An FPGA IP Business Model Finally Possible?

As featured in:
The IP-SoC conference panel, “IPs on FPGA: Strategy and Vision,” was a learning experience for me. Coming from the software and silicon/ASIC/ASSP worlds, I thought I had a pretty comprehensive view of all the various IP licensing models and their technical implementations. But I learned something new that makes me feel positive about the FPGA’s abilities to finally offer a robust market of third party IP. 

Topics: Interconnect economics FPGA IP