Arteris Articles

EE Times article, The Age of the Monster Chip

K. Charles Janac, President and CEO, at Arteris IP, authored this article on what is now defined as a "Monster Chip".

September 19, 2019 - by K. Charles Janac

What are the system designs that require a leap in SoC complexity? It’s not only big datacenter artificial intelligence (AI) chips, but also autonomous vehicles such as cars, trucks and drones; they are self-landing, reusable rockets; they are medical devices carrying out remote diagnostics; and they are connected machine tool controllers supporting smart manufacturing.

These chips are starting to be referred to as “Monster Chips” because of both the size and complexity.

Topics: semiconductor ADAS eetimes autonomous driving AI K. Charles Janac SoCs noc interconnect data center automation blockchain big chips

EE Times article, The Gatekeeper of a Successful Design is the Interconnect

K. Charles Janac, President and CEO, at Arteris IP, authored this article on how an effective interconnect makes delivering a complex SoC easier, more predictable, and less costly.

August 25, 2019 - by K. Charles Janac

An interconnect handles various types of traffic inside an SoC and is a mechanism for effective IP block integration. The interconnect is the most configurable IP in the SoC — typically changing many times during a project and nearly always changing between projects. It also plays a vital role in security and functional safety because it carries most of the SoC data and contains nearly all the SoC’s long wires and system-level services, including quality of service (QoS), visibility, physical awareness, and power management. The interconnect enables cache coherency in multiprocessor SoCs, high-performance and bandwidth levels in advanced driver assistance systems (ADAS) automotive chips and networking SoCs, and ultra-low power in long-running consumer devices.

Topics: semiconductor eetimes advanced driver assistance systems adas autonomous driving AI K. Charles Janac SoCs noc interconnect ML data center automation

Semiconductor Engineering: Chiplets, Faster Interconnects, More Efficiency

 Arteris IP's K. Charles Janac, president and CEO, chats with Ed Sperling at Hot Chips in this latest Semiconductor Engineering article:

Chiplets, Faster Interconnects, More Efficiency

August 22nd, 2019 - By Ed Sperling

Big chipmakers are turning to architectural improvements such as chipsets, faster throughput both on-chip and off-chip, and concentrating more work per operation or cycle, in order to ramp up processing speeds and efficiency.

 

“Everyone is struggling with CCIX,” said K. Charles Janac, president and CEO of Arteris IP. “If you have an accelerator and two coherent dies, there are too many corner cases to get it to work easily. But now you can use 3D interconnects to hook together a planar CPU and a planar I/O. So this looks like one system to the software, and you have inter-chip links between the network on chip and different die. That way you can support non-coherent and coherent read/write across two die. It makes the interconnect more valuable, but it also makes it more complicated.”

“The memory controller and the NoC will have to be much more tightly integrated,” said Janac. “The problem is that neither one understands the QoS of the entire chip, and there aren’t any independent memory controller companies left. But memory traffic has to be better integrated to make this work.”

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Topics: SoC ArterisIP FlexNoC ncore cache coherent interconnect semiconductor engineering K. Charles Janac noc interconnect Hot Chips

Semiconductor Engineering: Not Enough Respect for SoC Interconnect

K. Charles Janac, CEO at Arteris IP, shares his opinion in this week's blog appearing in Semiconductor Engineering:

Not Enough Respect for SoC Interconnect

 

July 30th, 2018 - By K. Charles Janac

Topics: SoC functional safety SoC security semiconductor advanced driver assistance systems adas flexnoc interconnect semiconductor engineering soc architecture AI arteris ip ips K. Charles Janac on-chip memory interconnects logic IP modules SoC assembly topologies 5G mobility QoS