Arteris Articles

SemiWiki: How Should I Cache Thee? Let Me Count the Ways

Kurt Shuler, VP Marketing at Arteris IP, updates Bernard Murphy (SemiWiki), on some of the interesting ways AI is driving caching in this new SemiWiki blog:

How Should I Cache Thee? Let Me Count the Ways

September 25th, 2019 - By Bernard Murphy

Caching is well-known as a method to increase processing performance and reduce power by reducing need for repeated accesses to main memory. What may be less well-known is how varied this technique has become, especially in and around AI accelerators. 

Caching intent largely hasn’t changed since we started using the concept – to reduce average latency in memory accesses and to reduce average power consumption in off-chip reads and writes. The architecture started out simple enough, a small memory close to a processor, holding most-recently accessed instructions and data at some level of granularity (e.g. a page). Caching is a statistical bet; typical locality of reference in the program and data will ensure that multiple reads and writes can be made very quickly to that nearby cache memory before a reference is made outside that range. When a reference is out-of-range, the cache must be updated by a slower access to off-chip main memory. On average a program runs faster because, on average, the locality of reference bet pays off.

You can learn more by visiting the Arteris IP Ncore Cache Coherent Interconnect IP webpage; http://www.arteris.com/ncore and the CodaCache Last Level Cache IP webpage; http://www.arteris.com/codacache-last-level-cache

Topics: SoC semiconductor automotive artificial intelligence ncore cache coherent interconnect semiwiki CodaCache kurt shuler noc interconnect ai accelerators

Semiconductor Engineering: In-System Networks Are Front And Center

 Arteris IP's Kurt Shuler, VP of Marketing, authored this article and offers his perspective on HotChips 2019 in this latest Semiconductor Engineering:

In-System Networks Are Front And Center

September 15th, 2019 - By Kurt Shuler

AI demands push innovation in design architectures and techniques.

 

This year’s HotChips conference at Stanford was all about artificial intelligence (AI) and machine learning (ML) and what particularly struck me, naturally because we’re in this business too, was how big a role on-chip networks played in some of the leading talks.

Giant leaps are being made in supporting new AI architectures, tuning them for optimum performance per milliwatt and embedding them effectively into traditional and novel SoC architectures.

You can learn more by reading my white paper titled, "Re-Architecting SoCs for the AI Era". Download is free; https://www.arteris.com/download-re-architecting-socs-for-the-ai-era

Topics: SoC functional safety ISO 26262 machine learning cache coherency semiconductor engineering AI kurt shuler noc interconnect SOTIF (ISO 21448 Hot Chips bigger chips

Semiconductor Engineering: Autonomous Vehicles Are Reshaping The Tech World

 Arteris IP's Kurt Shuler, VP of Marketing, comments on ISO 26262 and the need to add SOTIF for the unknown-unkown errors in this latest Semiconductor Engineering article:

Autonomous Vehicles Are Reshaping The Tech World

September 5th, 2019 - By Kevin Fogarty

Even before fully autonomous vehicles blanket the road there is major upheaval at all levels of the industry.

 

Until recently, the V-system testing of ISO 26262 has been the primary functional safety method for verification and validation. It will continue to play that role, according to Kurt Shuler, vice president of marketing at Arteris IP, but it will be supplemented by other types of testing such as SOTIF (safety of the intended functionality, ISO 21448).

“SOTIF was a little controversial,” Shuler said. “It almost didn’t get passed because of what I call the philosophical element. It is designed to find faults when things are working correctly, but it also finds errors that you don’t know about. The way it goes about that is a little different from the usual approach, but there are also standards coming from SAE and others from ISO, so there will be plenty of competition for this kind of challenge to be able to verify probabilistic systems.”

For more information, please visit our Resources page for free downloads of our technical papers; http://www.arteris.com/resources

Topics: SoC ISO 26262 autonomous driving ArterisIP FlexNoC semiconductor engineering AI kurt shuler noc interconnect SOTIF (ISO 21448

SemiWiki: AI, Safety and the Network

Kurt Shuler, VP Marketing at Arteris IP, and Bernard Murphy (SemiWiki) discuss, 'What is driving the boom in AI-centric design', in this new SemiWiki blog:

AI, Safety and the Network

September 4th, 2019 - By Bernard Murphy

You probably know that Arteris IP is very active in AI and safety, leveraging their central value in network-on-chip (NoC) architectures. Bernard Murphy of SemiWiki blogged on Kurt Shuler's front-to-back white-paper to walking us through the essentials of AI, particularly machine learning (ML) and its application for example in cars.

Kurt also highlights an interesting point about this rapidly evolving technology. As we build automation from the edge to the fog to the cloud, functionality, including AI, remains quite fluid between levels. Kurt points out that this is somewhat mirrored in SoC design. In both cases architecture is constrained by need to optimize performance and minimize power across the system through intelligent bandwidth allocation and data locality. And for safety-critical applications, design and verification for safety around intelligent features must be checked not only within and between SoCs in the car but also beyond, for example in V2x communication between cars and other traffic infrastructure.

You can learn more by downloading this Arteris IP white paper titled, Re-Architecting SoCs for the AI Era: https://semiwiki.com/automotive/274598-ai-safety-and-the-network/

Topics: SoC functional safety ISO 26262 semiconductor automotive ADAS machine learning artificial intelligence semiwiki kurt shuler flexnoc ai package noc interconnect